X4643, X4645

FN8123 Rev 0.00

Page 2 of 21

March 29, 2005

PIN CONFIGURATION

PIN FUNCTION

S1

VSS

VCC

SDA

SCL

3

2

4

1

6

7

5

8

S0

WP

RESET/RESET

VCC

S1

SCL

RESET/RESET

VSS

3

2

4

1

6

7

5

8

WP

SDA

S0

8-Pin JEDEC SOIC

8 Pin TSSOP

Pin

(SOIC)

Pin (TS-

SOP)

Name

Function

13

S0

Device Select Input

24

S1

Device Select Input

35

RESET/RESET

Reset Output

. RESET/RESET is an active LOW/HIGH, open drain output

which goes active whenever VCC falls below the minimum VCC sense level. It

will remain active until VCC rises above the minimum VCC sense level for

250ms. RESET/RESET goes active if the Watchdog Timer is enabled and SDA

remains either HIGH or LOW longer than the selectable Watchdog time out pe-

riod. A falling edge on SDA, while SCL is HIGH, resets the Watchdog Timer.

RESET/RESET goes active on power-up and remains active for 250ms after

the power supply stabilizes.

46

VSS

Ground

57

SDA

Serial Data.

SDA is a bidirectional pin used to transfer data into and out of the

device. It has an open drain output and may be wire ORed with other open

drain or open collector outputs. This pin requires a pull up resistor and the input

buffer is always active (not gated).

Watchdog Input.

A HIGH to LOW transition on the SDA (while SCL is HIGH) re-

starts the Watchdog timer. The absence of a HIGH to LOW transition within the

watchdog time out period results in RESET/RESET going active.

68

SCL

Serial Clock.

The Serial Clock controls the serial bus timing for data input and

output.

71

WP

Write Protect.

WP HIGH used in conjunction with WPEN bit prevents writes to

the control register.

82

VCC

Supply Voltage