ST72F262G2B6 datasheet(168/172 Pages) STMICROELECTRONICS

168 / 172 page

ST72260Gx, ST72262Gx, ST72264Gx

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16 KNOWN LIMITATIONS

16.1 ALL FLASH AND ROM DEVICES

16.1.1 16-bit timer PWM Mode

In PWM mode, the first PWM pulse is missed after

writing the value FFFCh in the OC12R register.In

PWM mode, the first PWM pulse is missed after

writing the value FFFCh in the OC1R register

(OC1HR, OC1LR). It leads to either full or no PWM

during a period, depending on the OLVL1 and

OLVL2 settings.

16.1.2

Clearing

active

interrupts

outside

interrupt routine

When an active interrupt request occurs at the

same time as the related flag or interrupt mask is

being cleared, the CC register may be corrupted.

Concurrent interrupt context

The symptom does not occur when the interrupts

are handled normally, i.e. when:

– The interrupt request is cleared (flag reset or in-

terrupt mask) within its own interrupt routine

– The interrupt request is cleared (flag reset or in-

terrupt mask) within any interrupt routine

– The interrupt request is cleared (flag reset or in-

terrupt mask) in any part of the code while this in-

terrupt is disabled

If these conditions are not met, the symptom can

be avoided by implementing the following se-

quence:

Perform SIM and RIM operation before and after

resetting an active interrupt request

Ex:

SIM

reset flag or interrupt mask

RIM

Nested interrupt context

The symptom does not occur when the interrupts

are handled normally, i.e. when:

– The interrupt request is cleared (flag reset or in-

terrupt mask) within its own interrupt routine

– The interrupt request is cleared (flag reset or in-

terrupt mask) within any interrupt routine with

higher or identical priority level

– The interrupt request is cleared (flag reset or in-

terrupt mask) in any part of the code while this in-

terrupt is disabled

If these conditions are not met, the symptom can

be avoided by implementing the following se-

quence:

PUSH CC

SIM

reset flag or interrupt mask

POP CC

16.1.3 I2C Multimaster

In multimaster configurations, if the ST7 I2C re-

ceives a START condition from another I2C mas-

ter after the START bit is set in the I2CCR register

and before the START condition is generated by

the ST7 I2C, it may ignore the START condition

from the other I2C master. In this case, the ST7

master will receive a NACK from the other device.

On reception of the NACK, ST7 can send a re-start

and Slave address to re-initiate communication

16.1.4 Functional EMS

The functional EMS (Electro Magnetic Susceptibil-

ity) severity level/behaviour class is 2B as defined

in application note AN1709.

Special care should be taken when designing the

PCB layout and firmware (refer to application

notes AN898, AN901 and AN1015) in sensitive

applications (that use switches for instance). For

more information refer to application note AN1637.

16.2 FLASH DEVICES ONLY

16.2.1 Execution of BTJX instruction

When testing the address $FF with the "BTJT" or

"BTJF" instructions, the CPU may perform an in-

correct operation when the relative jump is nega-

tive and performs an address page change.

To avoid this issue, including when using a C com-

piler, it is recommended to never use address

$00FF as a variable (using the linker parameter for

example).

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