ST72F262G2B6 datasheet(169/172 Pages) STMICROELECTRONICS

169 / 172 page

ST72260Gx, ST72262Gx, ST72264Gx

169/172

16.2.2 I/O Port B and C configuration

When using an external quartz crystal or ceramic

resonator, the fOSC2 clock may be disturbed be-

cause the device goes into reserved mode control-

led by Port B and C.

This happens with either one of the following con-

figurations:

PB1=0, PC2=1, PB3=0 while PLL option is both

disabled and PC4 is toggling

PB1=0, PC2=1, PB3=0, PC4=1 while PLL option

is enabled

This is detailed in the following table:

As a consequence, for cycle-accurate operations,

these configurations are prohibited in either input

or output mode.

Workaround:

To avoid this occurring, it is recommended to con-

nect one of these pins to GND (PC2 or PC4) or

VDD (PB1 or PB3).

16.2.3 16-bit Timer PWM mode

After a write instruction to the OCiHR register, the

output compare function is inhibited until the

OCiLR register is also written.

16.2.4 SPI Multimaster Mode

Multi master mode is not supported.

16.2.5 Internal RC oscillator with LVD

If the LVD is disabled, the internal RC oscillator

clock source cannot be used.

In ICP mode, new flash devices must be pro-

grammed with an external clock connected to the

OSC1 pin or using a crystal or ceramic resonator.

In the STVP7 programming tool software, select

the “OPTIONS DISABLED” mode.

16.2.6 External clock with PLL

The PLL option is not supported for use with exter-

nal clock source.

16.2.7 Halt mode power consumption with ADC

If the A/D converter is being used when Halt mode

is entered, the power consumption in Halt Mode

may exceed the maximum specified in the datash-

eet.

Workaround

Switch off the ADC by software (ADON=0) before

executing a HALT instruction.

16.2.8 Active Halt wake-up by external interrupt

External interrupts are not able to wake-up the

MCU from Active Halt mode. The MCU can only

exit from Active Halt mode by means of an MCC/

RTC interrupt or a reset.

Workaround

Use WAIT mode if external interrupt capability is

required in low power mode.

16.2.9 SCI Wrong Break duration

Description

A single break character is sent by setting and re-

setting the SBK bit in the SCICR2 register. In

some cases, the break character may have a long-

er duration than expected:

- 20 bits instead of 10 bits if M=0

- 22 bits instead of 11 bits if M=1.

In the same way, as long as the SBK bit is set,

break characters are sent to the TDO pin. This

may lead to generate one break more than expect-

ed.

Occurrence

The occurrence of the problem is random and pro-

portional to the baudrate. With a transmit frequen-

19200

baud

(fCPU=8MHz

and

SCI-

BRR=0xC9), the wrong break duration occurrence

is around 1%.

Workaround

If this wrong duration is not compliant with the

communication protocol in the application, soft-

ware can request that an Idle line be generated

before the break character. In this case, the break

duration is always correct assuming the applica-

tion is not doing anything between the idle and the

break. This can be ensured by temporarily disa-

bling interrupts.

The exact sequence is:

– Disable interrupts

– Reset and Set TE (IDLE request)

– Set and Reset SBK (Break Request)

– Re-enable interrupts

16.2.10

A/D

converter

accuracy

for

first

conversion

When the ADC is enabled after being powered

down (for example when waking up from HALT,

ACTIVE-HALT or setting the ADON bit in the AD-

CCSR register), the first conversion (8-bit or 10-

PLL PB1 PC2 PB3 PC4 Clock Disturbance

OFF

Tog

glin

Max. 2 clock cycles

lost at each rising or

falling edge of PC4

Max. 1 clock cycle

lost out of every 16

ST72F262G2B6 Datasheet(PDF) 169 Page - STMicroelectronics

ST72F262G2B6 Datasheet(HTML) 169 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL