ES9033 datasheet(26/103 Pages) ESS

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0.3.1

ES9033 Datasheet Information

ESS TECHNOLOGY, INC. 109 Bonaventura Drive, San Jose, CA 95134, USA Tel (408) 643-8800 WWW.ESSTECH.COM

The following list shows the various clocks of the ES9033 and the associated registers for configuration.

Analog DAC Clock

•

Reg 0[5] (ENABLE_ANALOG_DAC_CH2)

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Reg 0[4] (ENABLE_ANALOG_DAC_CH1)

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Reg 193[7] (PLL_BYP)

•

Reg 193[1] (SEL_PLL_IN)

•

Reg 193[0] (EN_PLL_CLKIN)

NSMOD Clock

The NSMOD clock is utilized by the HyperStream® II Noise Shaped MODulators.

•

Reg 0[3] (ENABLE_NSMOD)

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Reg 0[2] (ENABLE_DAC)

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Reg 193[7] (PLL_BYP)

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Reg 193[1] (SEL_PLL_IN)

•

Reg 193[0] (EN_PLL_CLKIN)

DAC Interpolation Path Clock

•

Reg 2[5:0] (SELECT_IDAC_NUM)

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Reg 0[2] (ENABLE_DAC)

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Reg 193[7] (PLL_BYP)

•

Reg 193[1] (SEL_PLL_IN)

•

Reg 193[0] (EN_PLL_CLKIN)

Master BCK and WS

•

Reg 37 (MASTER MODE CONFIG)

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Reg 38[6:4] (MASTER_WS_SCALE)

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Reg 3[6:0] (SELECT_MENC_NUM)

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Reg 0[2] (ENABLE_DAC)

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Reg 193[7] (PLL_BYP)

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Reg 193[1] (SEL_PLL_IN)

•

Reg 193[0] (EN_PLL_CLKIN)

DSD Clock

•

Reg 1[1] (ENABLE_DSD_DECODE)

TDM Clock

•

Reg 1[0] (ENABLE_TDM_DECODE)

DoP Clock

•

Reg 1[2] (ENABLE_DOP_DECODE)

•

Reg 1[0] (ENABLE_TDM_DECODE)

ES9033 Datasheet(PDF) 26 Page - ESS Technology,Inc

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