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Detailed Description

Transmission Latency

10-BitCode

TXP,TXN

REFCLK

10-BitCode

b9

TD(0–9)

Data Reception

Receiver Clock Select Mode

TLK1221

SLLS713 – FEBRUARY 2007

In the TBI mode, the transmitter portion registers incoming 10-bit-wide data words (8b/10b encoded data,

TD0–TD9) on the rising edge of REFCLK. REFCLK is also used by the serializer, which multiplies the clock by a

factor of 10, providing a signal that is fed to the shift register. The 8b/10b encoded data is transmitted

sequentially, bits 0 through 9, over the differential high-speed I/O channel.

Data transmission latency is defined as the delay from the initial 10-bit word load to the serial transmission of

bit 9. The minimum latency in TBI mode is 19 bit times. The maximum latency in TBI mode is 20 bit times.

Figure 1. Transmitter Latency, Full-Rate Mode

The receiver section deserializes the differential serial data. The serial data is retimed based on an interpolated

clock generated from the reference clock. The serial data is then aligned to the 10-bit word boundaries and

presented to the protocol controller along with the receive byte clocks (RBC0, RBC1).

The TLK1221 only supports TBI-mode operation with half-rate and full-rate clocks on RBC0 and RBC1. In TBI

mode, there are two user-selectable clock modes that are controlled by the RBCMODE terminal: 1) full-rate

clock on RBC0 and 2) half-rate clocks on RBC0 and RBC1.

Table 1. Mode Selection

RECEIVE BYTE CLOCK

RBCMODE

MODE

TLK1221

0

TBI half-rate

30–65 MHz

1

TBI full-rate

60–130 MHz

In the half-rate mode, two receive byte clocks (RBC0 and RBC1) are 180 degrees out of phase and operate at

one-half the data rate. The clocks are generated by dividing down the recovered clock. The received data is

output with respect to the two receive byte clocks (RBC0, RBC1), allowing a protocol device to clock the parallel

bytes using the RBC0 and RBC1 rising edges. For the outputs to the protocol device, byte 0 of the received data

is valid on the rising edge of RBC1. Refer to the timing diagram shown in Figure 2.

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