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TLV2264IDR Datasheet(PDF) 41 Page - STMicroelectronics

Part # TLV2264IDR
Description  ADVANCED LINCOMS RAIL-TO-RAIL OPERATIONAL AMPLIFIERS
PDF  55 Pages
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Manufacturer  STMICROELECTRONICS [STMicroelectronics]
Direct Link  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

TLV2264IDR Datasheet(HTML) 41 Page - STMicroelectronics

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TLV226x, TLV226xA
Advanced LinCMOS RAILTORAIL
OPERATIONAL AMPLIFIERS
SLOS186C − FEBRUARY 1997 − REVISED AUGUST 2006
41
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
APPLICATION INFORMATION
macromodel information
Macromodel information provided was derived using Microsim Parts
, the model generation software used
with Microsim PSpice
. The Boyle macromodel (see Note 5) and subcircuit in Figure 62 are generated using
the TLV226x typical electrical and operating characteristics at TA = 25°C. Using this information, output
simulations of the following key parameters can be generated to a tolerance of 20% (in most cases):
D Maximum positive output voltage swing
D Maximum negative output voltage swing
D Slew rate
D Quiescent power dissipation
D Input bias current
D Open-loop voltage amplification
D Unity-gain frequency
D Common-mode rejection ratio
D Phase margin
D DC output resistance
D AC output resistance
D Short-circuit output current limit
NOTE 5: G. R. Boyle, B. M. Cohn, D. O. Pederson, and J. E. Solomon, “Macromodeling of Intergrated Circuit Operational Amplifiers,” IEEE
Journal of Solid-State Circuits, SC-9, 353 (1974).
OUT
+
−
+
−
+
−
+
−
+
−
+
−
+
−
+
−
+
−
.SUBCKT TLV226x 1 2 3 4 5
C1
11
12
5.5E−12
C2
6
7
20.00E−12
DC
5
53
DX
DE
54
5
DX
DLP
90
91
DX
DLN
92
90
DX
DP
43DX
EGND
99
0
POLY (2) (3,0) (4,0) 0 .5 .5
FB
7
99
POLY (5) VB VC VE VLP
+ VLN 0 8.84E6 −10E6 10E6 10E6 −10E6
GA
6
0
11
12 62.83E−6
GCM
0
6
10
99 12.34E−9
ISS
3
10
DC 11.05E−6
HLIM
90
0
VLIM 1K
J1
11
2
10 JX
J2
12
1
10 JX
R2
6
9
100.0E3
RD1
60
11
15.92E3
RD2
60
12
15.92E3
R01
8
5
135
R02
7
99
135
RP
3
4
15.87E3
RSS
10
99
18.18E6
VAD
60
4
−.5
VB
9
0
DC 0
VC
3
53
DC .615
VE
54
4
DC .615
VLIM
7
8
DC 0
VLP
91
0
DC 1
VLN
0
92
DC 5.1
.MODEL DX D (IS=800.0E−18)
.MODEL JX PJF (IS=500.0E−15 BETA=325E−6
+ VTO=−.08)
.ENDS
VCC +
RP
IN −
2
IN +
1
VCC −
VAD
RD1
11
J1
J2
10
RSS
ISS
3
12
RD2
60
VE
54
DE
DP
VC
DC
4
C1
53
R2
6
9
EGND
VB
FB
C2
GCM
GA
VLIM
8
5
RO1
RO2
HLIM
90
DLP
91
DLN
92
VLN
VLP
99
7
Figure 62. Boyle Macromodel and Subcircuit
PSpice and Parts are trademarks of MicroSim Corporation.



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