SP6133 datasheet(13/20 Pages) SIPEX

13 / 20 page

Oct 24-06 Rev L

SP633 Synchronous Buck Controller

The power dissipation of the Schottky diode

isdeterminedby:

PDIODE = 2 • VF • Iout • TNOL • FS

where:

TNOL = non-overlap time between GH and GL.

VF = forward voltage of the Schottky diode.

Loop Compensation Design

The open loop gain of the whole system can

be divided into the gain of the error ampli-

fier,PWMmodulator,buckconverteroutput

stage, and feedback resistor divider. In or-

dertocrossoverattheselectedfrequency

FCO,thegainoftheerroramplifierhasto

compensate for the attenuation caused by

therestoftheloopatthisfrequency.

The goal of loop compensation is to manipu-

lateloopfrequencyresponsesuchthatits

gain crosses over 0db at a slope of -20db/

dec.Thefirststepofcompensationdesign

istopicktheloopcrossoverfrequency.High

crossover frequency is desirable for fast

transient response, but often jeopardizes

the system stability. Crossover frequency

should be higher than the ESR zero but

less than 1/5 of the switching frequency.

The ESR zero is contributed by the ESR

associated with the output capacitors and

canbedeterminedby:

ƒz(Esr) =

2π • Cout • REsr

The next step is to calculate the complex

conjugate poles contributed by the LC

outputfilter,

ƒp(Lc) =

2π •

√ L • COUT

When the output capacitors are of a Ceramic

Type,theSP6133EvaluationBoardrequires

aTypeIIIcompensationcircuittogiveaphase

boostof180°inordertocounteracttheeffects

of an under damped resonance of the output

filteratthedoublepolefrequency.

APPLICATION INFORMATION

(SRz2Cz2+1)(SR1Cz3+1)

(SRESRCOUT+ 1)

[S2LC

OUT+S(RESR+RDC) COUT+1]

VIN

SR1Cz2(SRz3Cz3+1)(SRz2Cp1+1)

VRAMP_PP

VOUT

(Volts)

VREF

(Volts)

Notes: R

ESR = Output Capacitor Equivalent Series Resistance.

DC = Output Inductor DC Resistance.

RAMP_PP = SP6132 Internal RAMP Amplitude Peak to Peak Voltage.

Condition: Cz2 >> Cp1 & R1 >> Rz3

Output Load Resistance >> R

ESR & RDC

VREF

(R1 + R2)

VOUT

VFBK

(Volts)

Type III Voltage Loop

Compensation

AMP (s) Gain Block

PWM Stage

PWM Gain

Block

Output Stage

OUT (s) Gain

Block

Voltage Feedback

FBK Gain Block

Figure 5: SP6133 Voltage

Mode Control Loop with

Loop Dynamic

Definitions:

REsr=OutputCapacitorEquivalentSeriesResistance

Rdc = Output Inductor DC Resistance

Vramp _ pp = SP633 internal RAMP Amplitude Peak to Peak Voltage

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