AD600JRZ-R7 datasheet(6/28 Pages) AD

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AD600/AD602

Rev. E | Page 6 of 28

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

VPOS

VNEG

REF

AD600/

AD602

–

C1HI

A1CM

A1OP

A2OP

A2CM

C2HI

C1LO

A1HI

A1LO

GAT1

A2LO

A2HI

C2LO

GAT2

Figure 2. Pin Configuration

Table 3. Pin Function Descriptions

Pin No.

Mnemonic

Description

C1LO

CH1 Gain-Control Input LO (Positive Voltage Reduces CH1 Gain)

A1HI

CH1 Signal Input HI (Positive Voltage Increases CH1 Output)

A1LO

CH1 Signal Input LO (Usually Connected to CH1 Input Ground)

GAT1

CH1 Gating Input (A Logic HI Shuts Off CH1 Signal Path)

GAT2

CH2 Gating Input (A Logic HI Shuts Off CH2 Signal Path)

A2LO

CH2 Signal Input LO (Usually Connected to CH2 Input Ground)

A2HI

CH2 Signal Input HI (Positive Voltage Increases CH2 Output)

C2LO

CH2 Gain-Control Input LO (Positive Voltage Reduces CH2 Gain)

C2HI

CH2 Gain-Control Input HI (Positive Voltage Increases CH2 Gain)

A2CM

CH2 Common (Usually Connected to CH2 Output Ground)

A2OP

CH2 Output

VNEG

Negative Supply for Both Amplifiers

VPOS

Positive Supply for Both Amplifiers

A1OP

CH1 Output

A1CM

CH1 Common (Usually Connected to CH1 Output Ground)

C1HI

CH1 Gain-Control Input HI (Positive Voltage Increases CH1 Gain)

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