AD1992ACPZ datasheet(14/20 Pages) AD

14 / 20 page

AD1992

Rev. 0 | Page 14 of 20

Note that the amplifier is capable of dc-coupled operation if the

circuit includes some means to account for this bias voltage.

AINL/

AINR

Figure 34. AC-Coupled Input Signal

Setting the Modulator Gain

The AD1992 modulator uses a combination of the input signal

and feedback from the power output stage to calculate its two-

state output pattern. The feedback input nodes are part of the

internal analog circuit that operates from the AVDD (nominal

5 V) power supply. Because the voltage measured at the power

outputs is nominally between 0 V and PVDD, and thus beyond

the 0 V to AVDD range, a voltage divider is required to scale the

feedback to an appropriate level.

Resistor voltage dividers should sense the voltage on each side

of the differential output and provide these feedback signals to

the modulator, as shown in Figure 35.

EXTERNAL COMPONENTS

OUTx+

OUTx–

PVDD

NFx+

NFx–

PGND

Figure 35. H-Bridge Configuration

The resistor values should satisfy the following equation to

maintain modulator stability.

635

Gain

Selecting a gain that meets this criterion ensures that the

modulator remains in a stable operating condition.

The ratio of the resistances sets the gain rather than the absolute

values. However, the dividers provide a path from the high

voltage supply to ground; therefore, the values should be large

enough to produce negligible loss due to quiescent current.

The chip contains a calibration circuit to minimize voltage

offsets at the speaker, which helps to minimize clicks and pops

when muting or unmuting. Optimal performance is achieved

for the offset calibration circuit when the feedback divider resistors

sum to 6 kΩ, that is, (R1 + R2) = 6 kΩ, and (R3 + R4) = 6 kΩ.

This fixed total resistance to ground eliminates the last free

variable and gives the following equations for the resistors:

21810

= R3 = 6000 − R2

Note that the gain previously mentioned applies to each side of

the differential output pair. Therefore, the total forward gain for

the modulator and output stage is twice that value. Recommended

resistor values for some common supply voltages are shown

in Table 10.

Table 10. Recommended Feedback Resistor Values

PVDD (V)

R1 (kΩ)

R2 (kΩ)

Voltage

Divider Gain

Differential

System Gain

4.18

1.82

3.30

6.60 (16.4 dB)

4.55

1.45

4.13

8.25 (18.3 dB)

4.79

1.21

4.95

9.90 (19.9 dB)

4.91

1.09

5.50

11.0 (20.8 dB)

Programmable Gain Amplifier (PGA)

The Σ-Δ modulator itself requires a fixed gain for a given value

of PVDD to maintain optimal stability. This gain can be appropriate,

but many applications require more gain to account for low

source signal levels. The AD1992 includes a programmable gain

amplifier (PGA) to boost the overall amplifier gain. The total gain

for the amplifier is the product of the modulator gain and the

PGA gain. PGA1 (Pin 31) and PGA0 (Pin 32) select one of four

PGA gain values, as shown in Table 11.

Table 11. PGA Gain Settings

PGA1

PGA0

PGA Gain

1 (0 dB)

2 (6 dB)

4 (12 dB)

8 (18 dB)

The AD1992 incorporates a single-ended-to-differential

converter for each channel in the analog front-end section.

The PGA is also part of this analog front-end, and it affects the

analog input signal before it enters the Σ-Δ modulator. The

PGA1 and PGA0 pins are continuously monitored and allow

the gain to be changed at any time.

POWER STAGE

The H-Bridge

The output stage of the AD1992 includes four integrated

MOSFET devices arranged in a full H-bridge, as shown in

Figure 35. The P-Type, high-side transistor of one leg and the

N-Type, low-side transistor of the opposite leg switch on and off

as a pair producing a total voltage swing across the load of

−PVDD to +PVDD. The drive is floating and differential, and it is

important that neither output terminal be shorted to ground.

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