AT90S1200 datasheet(21/71 Pages) ATMEL

21 / 71 page

AT90S1200

0838H–AVR–03/02

Figure 19. Timer/Counter0 Block Diagram

The 8-bit Timer/Counter0 can select clock source from CK, prescaled CK or an external

pin. In addition it can be stopped as de scribed in th e sp ecification fo r th e

Timer/Counter0 Control Register (TCCR0). The overflow status flag is found in the

Timer/Counter Interrupt Flag Register (TIFR). Control signals are found in the

Timer/Counter0 Control Register (TCCR0). The interrupt enable/disable settings for

Timer/Counter0 are found in the Timer/Counter Interrupt Mask Register (TIMSK).

When Timer/Counter0 is externally clocked, the external signal is synchronized with the

oscillator frequency of the CPU. To assure proper sampling of the external clock, the

minimum time between two external clock transitions must be at least one internal CPU

clock period. The external clock signal is sampled on the rising edge of the internal CPU

clock.

The 8-bit Timer/Counter0 features both a high-resolution and a high-accuracy usage

with the lower prescaling opportunities. Similarly, the high prescaling opportunities make

the Timer/Counter0 useful for lower speed functions or exact timing functions with infre-

quent actions.

Timer/Counter0 Control

• Bits 7..3 – Res: Reserved Bits

These bits are reserved bits in the AT90S1200 and always read as zero.

Bit

3210

$33

CS02

CS01

CS00

TCCR0

Read/Write

R/W

Initial Value

0000

AT90S1200 Datasheet(PDF) 21 Page - ATMEL Corporation