AT45DB021D-MU datasheet(38/52 Pages) ATMEL

38 / 52 page

3638B–DFLASH–02/07

AT45DB021D [Preliminary]

21.6

Reset Timing

Note:

The CS signal should be in the high state before the RESET signal is deasserted.

21.7

Command Sequence for Read/Write Operations for Page Size 256 Bytes (Except Status

21.8

Command Sequence for Read/Write Operations for Page Size 264 Bytes (Except Status

SCK

RESET

SO (OUTPUT)

HIGH IMPEDANCE

SI (INPUT)

tRST

tREC

tCSS

SI (INPUT)

CMD

8 bits

Page Address

(A17 - A8)

X X X X X X

X X

X X X X X X X X

LSB

X X X X X X X X

Byte/Buffer Address

(A7 - A0/BFA7 - BFA0)

MSB

6 Don’t Care

Bits

Page Address

(PA9 - PA0)

Byte/Buffer Address

(BA8 - BA0/BFA8 - BFA0)

SI (INPUT)

CMD

8 bits

X X X X X

X X X X

X X X

LSB

X X X X X X X X

MSB

5 Don’t Care

Bits

X X X X

AT45DB021D-MU Datasheet(PDF) 38 Page - ATMEL Corporation

AT45DB021D-MU Datasheet(HTML) 38 Page - ATMEL Corporation

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