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AT83C5103 Datasheet(PDF) 1 Page - ATMEL Corporation |
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AT83C5103 Datasheet(HTML) 1 Page - ATMEL Corporation |
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1 / 64 page  Rev. 4134C–8051–09/04 1 Features • 80C51 Compatible CPU Core High-speed Architecture • X2 Speed Improvement Capability (6 Clocks/Machine Cycle) • 16 MHz in Standard or X2 mode • 256 Bytes RAM • 256 Bytes XRAM • 12K Bytes ROM/OTP Program Memory • Two 16-bit Timer/Counters T0, T1 • 5 Channels Programmable Counter Array with High-speed Output, Compare/Capture, Pulse Width Modulation and Watchdog Timer Capabilities • SPI Interface (Master and Slave mode) • Interrupt Structure with: – 6 Interrupt Sources – 4 Interrupt Priority Levels • Power Supply: 3 - 5.5V • Temperature Range: Industrial (-40oC to 85oC), Automotive (-40oC to 125oC) • Package: SSOP16, SSOP24 Description The AT8xC5103 is a high-performance ROM/OTP version of the 80C51 8-bit Micro- controller in 16 and 24-pin packages. The AT8xC5103 contains a standard C51 CPU core with 12 Kbytes ROM/OTP pro- gram memory, 256 bytes of internal RAM, 256 bytes of extended internal RAM, a 5- sources 4-level interrupt system, two timer/counters and a SPI serial bus controller. The AT8xC5103 is also dedicated for analog interfacing applications. For this, it has a five channels Programmable Counter Array. In addition, the AT8xC5103 implements the X2 speed improvement mechanism. The X2 feature allows to keep the same CPU power at a divided by two oscillator frequency. The fully static design of the AT8xC5103 allows to reduce system power consumption by bringing the clock frequency down to any value, even DC, without loss of data. Low-pin Count 8-bit Microcontroller AT87C5103 AT83C5103 |
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