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MSP430F133IPM Datasheet(PDF) 53 Page - Texas Instruments |
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MSP430F133IPM Datasheet(HTML) 53 Page - Texas Instruments |
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53 / 83 page ![]() P3.3/UCLK0 P3IN.3 Pad Logic EN D P3OUT.3 P3DIR.3 P3SEL.3 UCLK.0 From USART0 0 1 0 1 DCM_UCLK SYNC MM STE STC UCLK0 To USART0 0: Input 1: Output P3.2/SOMI0 P3IN.2 Pad Logic EN D P3OUT.2 P3DIR.2 P3SEL.2 0 1 0 1 DCM_SOMI SYNC MM STE STC SO(MI)0 From USART0 (SO)MI0 To USART0 0: Input 1: Output 53 MSP430F149, MSP430F148, MSP430F147 MSP430F1491, MSP430F1481, MSP430F1471 MSP430F135, MSP430F133 www.ti.com SLAS272H – JULY 2000 – REVISED MAY 2018 Submit Documentation Feedback Product Folder Links: MSP430F149 MSP430F148 MSP430F147 MSP430F1491 MSP430F1481 MSP430F1471 MSP430F135 MSP430F133 Detailed Description Copyright © 2000–2018, Texas Instruments Incorporated Figure 6-16. Port P3 (P3.2) Diagram NOTE: UART mode: The UART clock can only be an input. If UART mode and UART function are selected, P3.3/UCLK0 is always an input. SPI slave mode: The clock applied to UCLK0 is used to shift data in and out. SPI master mode: The clock to shift data in and out is supplied to connected devices on pin P3.3/UCLK0 (in slave mode). Figure 6-17. Port P3 (P3.3) Diagram |
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