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RF7161

DS091006

7628 Thorndike Road, Greensboro, NC 27409-9421 · For sales or technical

support, contact RFMD at (+1) 336-678-5570 or sales-support@rfmd.com.

Power On Sequence

RF7161 Timing Diagram

Power Flattening and VBATT Tracking

The RF7161 has an integrated power flattening circuit that reduces the amount of current variation when a mismatch is pre-

sented to the output of the PA. When a mismatch is presented to the output of the PA its output impedance is varied and could

present a load that will increase outp ut power. As the output power increases so does the current consumption. The current

consumption can become very high if not monitored and limited. The power flattening circuit is integrated onto the CMOS con-

troller and requires no input from user.

Into a mismatch, the current varies as the phase c hanges. The power flattening circuit monitors current through an int ernal

sense resistor. As the current changes the loop is adjusted in order to maintain current. The result is flatter power and reduced

current into mismatch.

The RF7161 also incorporates a VBATT tracking feature that eliminates the need for the transceiver/baseband to regulate the

ramping signal as the supply voltage decreases. The internal circuit monitors the supply voltage and adjusts the ramping signal

such that the switching spectrum is minimally impacted.

Time

VBATT

GP0

GP1/GP2

TX_EN

VRAMP

GMSK Power On/Off Sequence

3.0 or 3.1V to 4.8V

>1.25V High Band

<0.5V Low Band

GP2<0.5V

>1.25V PA ON

1.8V for max Pout

0.25V for min Pout

Power On Sequence:

1. Apply VBATT

2. Apply GP0/GP1/GP2

3. Apply RFIN

4. Apply TX_EN

5. Apply minimum VRAMP (0.25V)

6. Ramp VRAMP for desired

output power

RFIN can be applied at any time.

For good transient response it

must be applied before power

ramp begins.

The Power Down Sequence is the

reverse order of the Power On

Sequence.

=2µs

=0µs

=0µs

=2µs

GP1>1.25V

RFIN

3 dBm