LMK6P datasheet(14/71 Pages) TI

14 / 71 page

over recommended operating conditions, typical temperature = 25°C, frequency output = 156.25 MHz, VDD = 3.3 V,

LVCMOS output capacitor load = 2.2 pF (unless otherwise specified)(4)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

LVCMOS - Clock Output Jitter

RMS jitter (integration BW: 12 kHz to 20

MHz)

Fout = 156.25 MHz

0.25

0.5

PN1k

Phase noise at 1 kHz offset

Fout = 156.25 MHz

–100

dBc/Hz

PN10k

Phase noise at 10 kHz offset

–128

dBc/Hz

PN100k

Phase noise at 100 kHz offset

–143

dBc/Hz

PN1M

Phase noise at 1 MHz offset

–150

dBc/Hz

PN10M

Phase noise at 10 MHz offset

–152

dBc/Hz

RMS jitter (integration BW: 12 kHz to 5

MHz)

Fout = 24 MHz

0.25

Fout = 25 MHz

0.25

Fout = 33.33 MHz

0.25

RMS jitter (integration BW: 12 kHz to 20

MHz)

Fout = 40 MHz

0.5

Fout = 50 MHz

0.4

Fout = 66.66 MHz

0.5

Fout = 74.25 MHz

0.3

0.5

Fout = 78 MHz

0.35

0.5

Fout = 100 MHz

0.35

0.5

Fout = 125 MHz

0.35

0.5

RPeriodJIT

T,RMS

RMS period jitter

Fout ≥ 25 MHz

1.5

RJITT,PK-

Peak-peak period jitter

Fout ≥ 25 MHz

(1)

DC Load condition

(2)

Measured using TI LMK6x Evaluation Module;

(3)

Refer to the Application Curves section for Rise time and fall time details for different capacitor load values.

(4)

The Jitter specifications are based on design and characterization

7.8 Timing Diagrams

VOD = VOH - VOL

OUTx_N

OUTx_P

VOUT-DIFF = 2 × VOD

0 V

20%

80%

VOH

VOL

Figure 7-1. Differential Output Voltage and Rise/Fall Time

LMK6C, LMK6D, LMK6H, LMK6P

SNAS826D – APRIL 2022 – REVISED FEBRUARY 2023

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