4

SY89529L

Micrel, Inc.

M9999-110405

hbwhelp@micrel.com or (408) 955-1690

Input/Output Pins

Pin Number

Pin Number

Pin Name

I/O

Pin Function

SOIC

TQFP

25,26

8, 9

XTAL1, XTAL2

Analog

These pins form an oscillator when connected to an external

Inputs

crystal. Either series or parallel-resonant crystals are

acceptable. Connect directly to the device.

10, 11

23, 24

SSC Control (0:1)

LVTTL

LVTTL-compatible spread-spectrum control pins. Data on

Inputs

control pins maintain device control. For spread-spectrum

operation, leave SSC_0 and SSC_1 pins floating (default is

spread ON). To reconfigure the device, simply change the

SSC and the device will respond dynamically.

SSC_0 = 24k

Ω pullup. SSC_1 = 24kΩ pulldown

16, 17

30, 31

FOUT, /FOUT

Differential

Differential, LVPECL clock outputs. These outputs must be

terminated to V

23

6

LOOP_FILTER

Analog I/O

Used for the R//C PLL loop filter. (see Figure 2.)

24

7

LOOP_REF

Analog I/O

Provides the reference voltage for the PLL. (see Figure 2).

13

27

TEST INPUT

LVTTL

Pin is used for test and debug purposes. Is intended to be

Inputs

left floating in production environment. Programmed as

input in PLL-bypass mode. Pin includes an internal 24k

Ω

pullup resistor.

Power Supply Pins

Pin Number

Pin Number

Pin Name

I/O

Pin Function

SOIC

TQFP

14, 27

10, 28

V

Logic

3.3V LVTTL core logic power-supply pins. Connect each

Power

pin directly to the logic-supply plane and use proper

bypassing at each pin as close to the pin as possible; Ferrite

bead in parallel with 1

µF//0.01µF capacitors. (see Figure 5

for typical bypass circuit.)

22

5

ANALOG_ V

CC

PLL

3.3V PLL core supply pin. Must be a noise free supply.

Power

Bypass as close to the pin as possible; ferrite bead in

parallel with 1

typical bypass circuit.)

18

32

V

CC_OUT

Output

This is the positive power supply reference for the LVPECL

Power

outputs (FOUT and /FOUT). See Figure 5 for typical bypass

circuit.

12

26

GND_TTL

Logic

This is the ground pin for for the TTL control logic. Normally

connected to the logic ground.

21

4

GND_ANALOG

Analog

This is the ground pin for the PLL Core. Normally connected

GND

to a quiet, noise-free ground plane for low jitter perfomance.

15

29

GND_OUTPUT

Output

Ground for differential outputs. Normally connected to the

GND

logic ground plane.

No Connect Pins

Pin Number

Pin Number

Pin Name

I/O

Pin Function

SOIC

TQFP

1, 2, 3, 4, 5

1, 2, 3, 11, 12, 13

NC

No

Pins are high-impedance, low leakage and are not used by

6, 7, 8, 9, 19

14, 15, 16, 17, 18

Connect

internal circuits of the device. These pins are intended to be

20, 28

19, 20, 21, 22, 25

left floating in production.

PIN DESCRIPTIONS