SN74LVC8T245DBR datasheet(2/20 Pages) TI

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DESCRIPTION/ORDERING INFORMATION (CONTINUED)

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SN74LVC8T245

8-BIT DUAL-SUPPLY BUS TRANSCEIVER

WITH CONFIGURABLE VOLTAGE TRANSLATION AND 3-STATE OUTPUTS

SCES584A – JUNE 2005 – REVISED AUGUST 2005

The SN74LVC8T245 is designed for asynchronous communication between two data buses. The logic levels of

the direction-control (DIR) input and the output-enable (OE) input activate either the B-port outputs or the A-port

outputs or place both output ports into the high-impedance mode. The device transmits data from the A bus to

the B bus when the B-port outputs are activated, and from the B bus to the A bus when the A-port outputs are

activated. The input circuitry on both A and B ports is always active and must have a logic HIGH or LOW level

applied to prevent excess ICC and ICCZ.

The SN74LVC8T245 is designed so that the control pins (DIR and OE) are supplied by VCCA.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,

preventing damaging current backflow through the device when it is powered down.

The VCC isolation feature ensures that if either VCC input is at GND, all outputs are in the high-impedance state.

To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup

resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

FUNCTION TABLE(1)

(EACH 8-BIT SECTION)

CONTROL INPUTS

OUTPUT CIRCUITS

OPERATION

DIR

A PORT

B PORT

Enabled

Hi-Z

B data to A bus

Hi-Z

Enabled

A data to B bus

Hi-Z

Isolation

(1)

Input circuits of the data I/Os are always active.

LOGIC DIAGRAM (POSITIVE LOGIC)

SN74LVC8T245DBR Datasheet(PDF) 2 Page - Texas Instruments