Data Sheet

AD45335

SPECIFICATIONS

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Rev. 0 | 5 of 16

TIMING CHARACTERISTICS

VPP = 55 V to 225 V; 4.75 ≤ V+ ≤ 5.25 V; 4.75 V ≤ AVCC ≤ 5.25 V; 2.7 V ≤ DVCC ≤ 5.25 V; PGND = AGND = DGND = DAC_GND = 0 V;

AVCC and V+ must exceed REF_IN by 1.15 V minimum; 1 V ≤ REF_IN ≤ 4.096 V; –10°C ≤ TA ≤ +85°C, unless otherwise noted.

Table 2. Timing Characteristics

Parameter1, 2, 3

Max

Min

Unit

Test Conditions/Comments

fUPDATE

1.2

MHz

Channel update rate

fCLKIN

30

MHz

SCLK frequency

t1

13

ns

SCLK high pulse width

t2

13

ns

SCLK low pulse width

t3

15

ns

SYNC falling edge to SCLK falling edge setup time

t4

50

ns

SYNC low time

t5

10

ns

SYNC high time

t6

10

ns

DIN setup time

t7

5

ns

DIN hold time

t8

200

ns

19th SCLK falling edge to SYNC falling edge for next write

t9

20

ns

RESET pulse width

1 See Figure 2.

2 Guaranteed by design and characterization, not production tested.

3 All input signals are specified with tr = tf = 5 ns (10% to 90% of DVCC) and timed from a voltage level of (VIL + VIH)/2.

Figure 2. Serial Interface Timing Diagram