D A TA

SH EE T

January 23, 2007 27546A6

Am29SL800D

39

ERASE AND PROGRAMMING PERFORMANCE

Notes:

1.

Typical program and erase times assume the following conditions: 25

assume checkerboard pattern.

2.

3.

The typical chip programming time is considerably less than the maximum chip programming time listed, since most bytes program faster

than the maximum program times listed.

4.

In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h before erasure.

5.

System-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program command. See Table 5 for further

information on command definitions.

6.

The device has a minimum guaranteed erase and program cycle endurance of 1,000,000 cycles.

Notes:

1.

Sampled, not 100% tested.

2.

Table 16.

Erase and Programming Performance

Parameter

Typ (Note 1)

Max (Note 2)

Unit

Comments

Sector Erase Time

0.7

15

s

Excludes 00h programming prior

to erasure (Note 4)

Chip Erase Time

14

s

Byte Programming Time

5

150

µs

Excludes system level overhead

(Note 5)

Word Programming Time

7

210

µs

Chip Programming Time

(Note 3)

Byte Mode

5.3

16

s

Word Mode

3.7

11

s

Table 17.

Latchup Characteristics

Description

Min

Max

(including A9, OE#, and RESET#)

–1.0 V

11.0 V

–0.5 V

–100 mA

+100 mA

Table 18.

TSOP Pin Capacitance

Parameter Symbol

Parameter Description

Test Setup

Typ

Max

Unit

Input Capacitance

6

7.5

pF

Output Capacitance

8.5

12

pF

Control Pin Capacitance

7.5

9

pF

Table 19.

Data Retention

Parameter

Test Conditions

Min

Unit

Minimum Pattern Data Retention Time

150

°C

10

Years

125

°C

20

Years