COM20019I-HT datasheet(49/65 Pages) SMSC

49 / 65 page

Low Cost ARCNET (ANSI 878.1) Controller with 2K x 8 On-Board RAM

SMSC COM20019I

Page 49

Rev. 03-07-06

DATASHEET

Figure 8.2 - MULTIPLEXED BUS, 80XX-LIKE CONTROL SIGNALS; READ CYCLE

AD0-AD2,

VALID

nCS

ALE

VALID DATA

t2,

D3-D7

nRD

t10

nWR

t13

t11

t12

Note 3

Note 2

MUST BE: RBUSTMG bit = 0

Parameter

min

max

units

Address Setup to ALE Low

Address Hold from ALE Low

nCS Setup to ALE Low

nCS Hold from ALE Low

ALE Low to nRD Low

nRD Low to Valid Data

nRD High to Data High Impedance

Cycle Time (nRD Low to Next Time Low)

4TARB

ALE High Width

ALE Low Width

nRD Low Width

nRD High Width

nWR

to nRD Low

t10

t11

t12

t13

The Microcontroller typically accesses the COM20019 on every other cycle.

Therefore, the cycle time specified in the microcontroller's datasheet

should be doubled when considering back-to-back COM20019 cycles.

Note 1:

TARB is the Arbitration Clock Period

TARB is identical to Topr if SLOW ARB = 0

TARB is twice Topr if SLOW ARB = 1

Topr is the period of operation clock. Same as the XTAL1 period.

Note 2:

Read cycle for Address Pointer Low/High Registers occurring after a read from

Data Register requires a minimum of 5TARB from the trailing edge of nRD to the

leading edge of the next nRD.

Note 3:

Read cycle for Address Pointer Low/High Registers occurring after a write to

Data Register requires a minimum of 5TARB from the trailing edge of nWR to the

leading edge of nRD.

COM20019I-HT Datasheet(PDF) 49 Page - SMSC Corporation

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