COM20022I3V-HT datasheet(39/83 Pages) SMSC

39 / 83 page

10 Mbps ARCNET (ANSI 878.1) Controller with 2Kx8 On-Board RAM

Datasheet

SMSC COM20022I 3V

Page 39

Revision 02-27-06

DATASHEET

Table 6.8 - Address Pointer High Register

BIT

BIT NAME

SYMBOL

DESCRIPTION

Read Data

RDDATA

This bit tells the COM20022I 3V whether the following

access will be a read or write. A logic "1" prepares the

device for a read, a logic "0" prepares it for a write.

Auto Increment

AUTOINC

This bit controls whether the address pointer will

increment automatically. A logic "1" on this bit allows

automatic increment of the pointer after each access,

while a logic "0" disables this function. Please refer to the

Sequential Access Memory section for further detail.

5-4

(Reserved)

These bits are undefined.

DMA Enable

DMAEN

This bit is used to Disable/Enable the assertion of the

DMA Request (DREQ pin) after writing the Address

Pointer Low register. DMAEN=0: Disable (Default).

DMAEN=1: Enable the assertion of the DREQ pin after

writing the Address Pointer Low register. Writing

DMAEN=0 during the DMA operation will negate the

DREQ pin immediately. The DMA operation is terminated

immediately after the next DACK pin negation. The

inverting signal of DAMEN is the Interrupt source signal

DMAEND. The DMAEN bit is cleared automatically by

finishing the DMA. If the DMAEND bit in the Mask register

is not masked, the Interrupt occurs by finishing the DMA

operation.

2-0

Address 10-8

A10-A8

These bits hold the upper three address bits which

provide addresses to RAM.

Table 6.9 - Address Pointer Low Register

BIT

BIT NAME

SYMBOL

DESCRIPTION

7-0

Address 7-0

A7-A0

SWAP

These bits hold the lower 8 address bits which provide the

addresses to RAM.

When 16 bit access is enabled, (W16=1), A0 becomes the

SWAP bit. Swap bit is undefined after a hardware reset.

The swap bit must be set before W16 bit is set to “1”. The

swap bit is used to swap the upper and lower data byte.

The swap bit influences both CPU cycle and DMA cycle.

See Table Below.

Detected Host

Interface Mode

Swap Bit

D15-D8

D7-D0

Intel 80xx Mode

Odd

Even

(RD, WR Mode)

Even

Odd

Motorola 68xx Mode

Even

Odd

(DIR, DS Mode)

Odd

Even

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