AM29F160DB75EC datasheet(22/47 Pages) SPANSION

22 / 47 page

Am29F160D

Am29F160D_00_D6 November 2, 2006

D A TA SH EE T

Note: See the appropriate Command Definitions table for

program command sequence.

Figure 3.

Program Operation

Chip Erase Command Sequence

Chip erase is a six-bus-cycle operation. The chip erase

command sequence is initiated by writing two unlock

cycles, followed by a set-up command. Two additional

unlock write cycles are then followed by the chip erase

command, which in turn invokes the Embedded Erase

algorithm. The device does not require the system to

preprogram prior to erase. The Embedded Erase algo-

rithm automatically preprograms and verifies the entire

memory for an all zero data pattern prior to electrical

erase. The system is not required to provide any con-

trols or timings during these operations. The Command

Definitions table shows the address and data require-

ments for the chip erase command sequence.

Any commands written to the chip during the Embed-

ded Erase algorithm are ignored. Note that a hardware

reset during the chip erase operation immediately ter-

minates the operation. The Chip Erase command se-

quence should be reinitiated once the device returns to

reading array data, to ensure data integrity.

The system can determine the status of the erase

operation by using DQ7, DQ6, DQ2, or RY/BY#. See

Write Operation Status‚ on page 23 for information

on these status bits. When the Embedded Erase al-

gorithm is complete, the device returns to reading

array data and addresses are no longer latched.

Figure 4, on page 21 illustrates the algorithm for the

erase operation. See the Erase/Program Operations

tables in “AC Characteristics” for parameters, and to

the Chip/Sector Erase Operation Timings for timing

waveforms.

Sector Erase Command Sequence

Sector erase is a six bus cycle operation. The sector

erase command sequence is initiated by writing two un-

lock cycles, followed by a set-up command. Two addi-

tional unlock write cycles are then followed by the

address of the sector to be erased, and the sector

erase command. The Command Definitions table

shows the address and data requirements for the sec-

tor erase command sequence.

The device does not require the system to preprogram

the memory prior to erase. The Embedded Erase algo-

rithm automatically programs and verifies the sector for

an all zero data pattern prior to electrical erase. The

system is not required to provide any controls or tim-

ings during these operations.

After the command sequence is written, a sector erase

time-out of 50 µs begins. During the time-out period,

additional sector addresses and sector erase com-

mands may be written. Loading the sector erase buffer

may be done in any sequence, and the number of sec-

tors may be from one sector to all sectors. The time be-

tween these additional cycles must be less than 50 µs,

otherwise the last address and command might not be

accepted, and erasure may begin. It is recommended

that processor interrupts be disabled during this time to

ensure all commands are accepted. The interrupts can

be re-enabled after the last Sector Erase command is

written. If the time between additional sector erase

commands can be assumed to be less than 50 µs, the

system need not monitor DQ3. Any command other

than Sector Erase or Erase Suspend during the

time-out period resets the device to reading array

data. The system must rewrite the command sequence

and any additional sector addresses and commands.

The system can monitor DQ3 to determine if the sector

erase timer has timed out. (See the DQ3: Sector Erase

Timer‚ on page 25 section.) The time-out begins from

the rising edge of the final WE# pulse in the command

sequence.

Once the sector erase operation begins, only the Erase

Suspend command is valid. All other commands are ig-

nored. Note that a hardware reset during the sector

erase operation immediately terminates the operation.

START

Write Program

Command Sequence

Data Poll

from System

Verify Data?

Yes

Last Address?

Yes

Programming

Completed

Increment Address

Embedded

Program

algorithm

in progress

AM29F160DB75EC Datasheet(PDF) 22 Page - SPANSION

AM29F160DB75EC Datasheet(HTML) 22 Page - SPANSION

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47

Datasheet Download

Link URL