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IR3084A Datasheet(PDF) 8 Page - International Rectifier |
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IR3084A Datasheet(HTML) 8 Page - International Rectifier |
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8 / 45 page  IR3084A Page 8 of 45 10/30/2006 PWM Control Method The PWM block diagram of the XPhaseTM architecture is shown in Figure 3. Feed íforward voltage mode control with trailing edge modulation is used. A high ígain wideíbandwidth voltage type error amplifier in the Control IC is used for the voltage control loop. An external RC circuit connected to the input voltage and ground is used to program the slope of the PWM ramp and to provide the feed íforward control at each phase. The PWM ramp slope will change with the input voltage and automatically compensate for changes in the input voltage. The input voltage can change due to variations in the silver box output voltage or due to drops in the PCB related to changes in load current. 200 OHM VSETPT RVSETPT RCS PWM COMPARATOR GND VOUT RVFB SYSTEM REFERENCE VOLTAGE VBIAS + - VBIAS REGULATOR VDAC BIASIN PWMRMP CLOCK PULSE GENERATOR DACIN RAMP DISCHARGE CLAMP ENABLE VOSNS+ RAMPIN+ VOSNS- RAMPIN- ISHARE VOSNS- RDRP VDRP IIN SCOMP O% DUTY CYCLE COMPARATOR VDRP AMP VDAC IOFFSET + - GATEH CSIN+ GATEL EAIN CSIN- VPEAK 50% DUTY CYCLE RAMP GENERATOR VVALLEY RMPOUT RRAMP1 RRAMP2 CURRENT SENSE AMP RESET DOMINANT PWM LATCH S SHARE ADJUST ERROR AMP X34 R ERROR AMP RAMP SLOPE ADJUST IROSC EAOUT X 0.91 FB CONTROL IC COUT 20mV + - 10K + - + - 10K RRAMP1 CCS RCS RRAMP2 BIASIN RAMPIN- EAIN ISHARE PWMRMP SCOMP RAMPIN+ CSIN+ GATEH DACIN CSIN- GATEL VIN PHASE IC PHASE IC PWM LATCH CURRENT SENSE AMP SHARE ADJUST ERROR AMP X34 RESET DOMINANT S R CLOCK PULSE GENERATOR 20mV PWM COMPARATOR ENABLE RAMP SLOPE ADJUST RAMP DISCHARGE CLAMP SYSTEM REFERENCE VOLTAGE O% DUTY CYCLE COMPARATOR X 0.91 CCS CSCOMP CPWMRMP RPWMRMP CSCOMP CPWMRMP RPWMRMP Figure 3 – IR3084A PWM Block Diagram Frequency and Phase Timing Control The oscillator is located in the Control IC and its frequency is programmable from 150kHz to 1MHZ by an external resistor. The output of the oscillator is a 50% duty cycle triangle waveform with peak and valley voltages of approximately 4.8V and 0.9V. This signal is used to program both the switching frequency and phase timing of the Phase ICs. The Phase IC is programmed by resistor divider RRAMP1 and RRAMP2 connected between the VBIAS reference voltage and the Phase IC LGND pin. A comparator in the Phase ICs detects the crossing of the oscillator waveform with the voltage generated by the resistor divider and triggers a clock pulse that starts the PWM cycle. The peak and valley voltages track the VBIAS voltage reducing potential Phase IC timing errors. Figure 4 shows the Phase timing for an 8 phase converter. Note that both slopes of the triangle waveform can be used for synchronization by swapping the RAMP + and – pins. |
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