P80CL410 datasheet(34/60 Pages) PHILIPS

34 / 60 page

1997 Apr 10

Philips Semiconductors

Product speciﬁcation

Low voltage 8-bit microcontrollers with

I2C-bus

P80CL410; P83CL410

16 RESET

To initialize the P8xCL410 a reset is performed by either of

three methods:

• Applying an external signal to the RST pin

• Via Power-on-reset circuitry.

A reset leaves the internal registers as shown in

Chapter 17. The reset state of the port pins is

mask-programmable and can be defined by the user.

16.1

External reset using the RST pin

The reset input for the P8xCL410 is RST. A Schmitt trigger

is used at the input for noise rejection. The output of the

Schmitt trigger is sampled by the reset circuitry every

machine cycle. A reset is accomplished by holding the

RST pin HIGH for at least two machine cycles

(24 oscillator periods) while the oscillator is running.

The CPU responds by executing an internal reset. Port

pins adopt their reset state immediately after the RST goes

HIGH. During reset, ALE and PSEN are held HIGH.

The external reset is asynchronous to the internal clock.

The RST pin is sampled during state 5, phase 2 of every

machine cycle. After a HIGH is detected at the RST pin, an

internal reset is repeated until RST goes LOW.

The internal RAM is not affected by reset. When VDD is

turned on, the RAM contents are indeterminate.

16.2

Power-on-reset

The device contains on-chip circuitry which switches the

port pins to the customer defined logic level as soon as

VDD exceeds 1.3 V; if the mask option ‘ON’ has been

chosen. As soon as the minimum supply voltage is

reached, the oscillator will start up. However, to ensure

that the oscillator is stable before the controller starts, the

clock signals are gated away from the CPU for a further

1536 oscillator periods. During that time the CPU is held in

a reset state. A hysteresis of approximately 50 mV at a

typical power-on switching level of 1.3 V will ensure

correct operation (see Fig.20).

The on-chip Power-on-reset circuitry can also be switched

off via the mask option ‘OFF’. This option reduces the

Power-down current to typically 800 nA and can be

chosen if external reset circuitry is used. For applications

not requiring the internal reset, option ‘OFF’ should be

chosen.

An automatic reset can be obtained by connecting the RST

pin to VDD via a 10 µF capacitor. At power-on, the voltage

on the RST pin is equal to VDD minus the capacitor voltage,

and decreases from VDD as the capacitor charges through

the internal resistor (RRST) to ground. The larger the

capacitor, the more slowly VRST decreases. VRST must

remain above the lower threshold of the Schmitt trigger

long enough to effect a complete reset. The time required

is the oscillator start-up time, plus 2 machine cycles.

The Power-on-reset circuitry is shown in Fig.19.

Fig.18 Reset configuration.

handbook, halfpage

MLA580

SCHMITT

TRIGGER

RESET

CIRCUITRY

RST

Fig.19 Recommended Power-on-reset circuitry.

handbook, halfpage

VDD

RST

µF

R RST

MBK024

P80CL410

P83CL410

P80CL410 Datasheet(PDF) 34 Page - NXP Semiconductors

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