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PCF85063AT/AAZ Datasheet(PDF) 31 Page - NXP Semiconductors

Part # PCF85063AT/AAZ
Description  Tiny Real-Time Clock/calendar with alarm function and I2C-bus
PDF  55 Pages
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Manufacturer  NXP [NXP Semiconductors]
Direct Link  http://www.nxp.com
Logo NXP - NXP Semiconductors

PCF85063AT/AAZ Datasheet(HTML) 31 Page - NXP Semiconductors

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NXP Semiconductors
PCF85063A
Tiny Real-Time Clock/calendar with alarm function and I2C-bus
S
1
0
1
0
0
0
1
1
A
DATA BYTE
LAST DATA BYTE
A
A
P
acknowledge
from PCF85063A
auto increment
memory register address
auto increment
memory register address
acknowledge
from master
slave address
read bit
0 to n data bytes
no acknowledge
aaa-004436
S
1
0
1
0
0
0
1
0
A
A
P
acknowledge
from PCF85063A
acknowledge
from PCF85063A
set register
address
read register
data
slave address
write bit
register address
00h to 11h
STOP
For multimaster configurations and to fasten the communication, the STOP-START sequence can be replaced by a
repeated START (Sr).
Figure 23. Master reads after setting register address (write register address; READ data)
8.5.2.1 I2C-bus error recovery technique
Slave devices like the PCF85063A use a state machine to implement the I2C protocol and expect a certain
sequence of events to occur to function properly. Unexpected events at the I2C master can wreak havoc with
the slaves connected on the bus. However, it is usually possible to recover deterministically to a known bus
state with careful protocol manipulation.
A deterministic method to clear this situation if SDA is stuck LOW (it effectively blocks any other I2C-bus
transaction, once the master recognizes a ‘stuck bus’ state), is for the master to blindly transmit nine clocks on
SCL. If the slave was transmitting data or acknowledging, nine or more clocks ensures the slave state machine
returns to a known, idle state since the protocol calls for eight data bits and one ACK bit. It does not matter
when the slave state machine finishes its transmission; extra clocks are recognized as STOP conditions.
With careful design of the bus master error recovery firmware, many I2C-bus protocol problems can be avoided.
S/W considerations: NXP recommends customers allow for S/W reset capability to enable the bus error
recovery technique. The 9-clock pulse method as described above involves a bus-master capable of providing
such a signal.
Further comments/additional information are available in [9] and [8]"UM10204".
PCF85063A
All information provided in this document is subject to legal disclaimers.
© 2023 NXP B.V. All rights reserved.
Product data sheet
Rev. 7.1 — 8 November 2023
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