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CDCD5704PW Datasheet(PDF) 7 Page - Texas Instruments |
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CDCD5704PW Datasheet(HTML) 7 Page - Texas Instruments |
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7 / 19 page  www.ti.com FUNCTIONAL DESCRIPTION OF THE LOGIC PLL Multiplication Factor Selection Modes of Operation CDCD5704 SCAS823 – DECEMBER 2006 Output Frequency (MHz) Multiplication Mult2 Mult1 Mult0 Factor REFCLK = 100 MHz REFCLK = 133 MHz 0 0 0 3 300 400 0(1) 0(1) 1(1) 4(1) 400 533 0 1 0 5 500 667 0 1 1 6 600 800(2) 1 0 0 8 800(2) –(2) 1 0 1 9/2 450 600 1 1 0 15/2 750(2) –(2) 1 1 1 15/4 375 500 (1) Default settings after power up (2) Output at this frequency does not conform to all the ac device characteristics in the Device Characteristics table, or ouput frequency is not supported. EN BYPASS Reg-Test RegA RegB RegC RegD CLK0 CLK1 CLK2 CLK3 L X X X X X X HI-Z HI-Z HI-Z HI-Z H X 1 X X X X RESERVED FOR VENDOR TEST H L 0 X X X X REFCLK REFCLK REFCLK REFCLK H H 0 0 0 0 0 HI-Z HI-Z HI-Z HI-Z H H 0 1 0 0 0 PLL CLK HI-Z HI-Z HI-Z H H 0 0 1 0 0 HI-Z PLL CLK HI-Z HI-Z H H 0 1 1 0 0 PLL CLK PLL CLK HI-Z HI-Z H H 0 0 0 1 0 HI-Z HI-Z PLL CLK HI-Z H H 0 1 0 1 0 PLL CLK HI-Z PLL CLK HI-Z H H 0 0 1 1 0 HI-Z PLL CLK PLL CLK HI-Z H H 0 1 1 1 0 PLL CLK PLL CLK PLL CLK HI-Z H H 0 0 0 0 1 HI-Z HI-Z HI-Z PLL CLK H H 0 1 0 0 1 PLL CLK HI-Z HI-Z PLL CLK H H 0 0 1 0 1 HI-Z PLL CLK HI-Z PLL CLK H H 0 1 1 0 1 PLL CLK PLL CLK HI-Z PLL CLK H H 0 0 0 1 1 HI-Z HI-Z PLL CLK PLL CLK H H 0 1 0 1 1 PLL CLK HI-Z PLL CLK PLL CLK H H 0 0 1 1 1 HI-Z PLL CLK PLL CLK PLL CLK H H 0(1) 1(1) 1(1) 1(1) 1(1) PLL CLK PLL CLK PLL CLK PLL CLK (1) Default settings after power up 7 Submit Documentation Feedback |
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