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TMS320DM647 Datasheet(PDF) 1 Page - Texas Instruments |
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TMS320DM647 Datasheet(HTML) 1 Page - Texas Instruments |
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1 / 166 page  www.ti.com 1 TMS320DM647/TMS320DM648 Digital Media Processor 1.1 Features TMS320DM647/TMS320DM648 Digital Media Processor SPRS372 – MAY 2007 • High-Performance Digital Media Processor • C64x+ L1/L2 Memory Architecture (DM647/DM648) – 256K-bit (32K-byte) L1P Program Cache – 720, 900-MHz C64x+™ Clock Rate [Direct Mapped] – 1.39, 1.11-ns Instruction Cycle Time – 256K-bit (32K-byte) L1D Data Cache [2-Way Set-Associative] – 5760, 7200 MIPS – 2M-bit/256K-byte (DM647) or – Eight 32-Bit C64x+ Instructions/Cycle 4M-Bit/512K-byte) (DM648) L2 Unified – Fully Software-Compatible With Mapped RAM/Cache [Flexible Allocation] C64x/Debug • Supports Little Endian Mode Only – Commercial Temperature Ranges • Five Configurable Video Ports • VelociTI.2™ Extensions to VelociTI™ – Providing a Glueless I/F to Common Video Advanced Very-Long-Instruction-Word (VLIW) Decoder and Encoder Devices TMS320C64x+™ DSP Core – Supports Multiple Resolutions/Video Stds – Eight Highly Independent Functional Units With VelociTI.2 Extensions: • VCXO Interpolated Control Port (VIC) • Six ALUs (32-/40-Bit), Each Supports – Supports Audio/Video Synchronization Single 32-bit, Dual 16-bit, or Quad 8-bit • External Memory Interfaces (EMIFs) Arithmetic per Clock Cycle – 32-Bit DDR2 SDRAM Memory Controller • Two Multipliers Support Four 16 x 16-bit With 256M-Byte Address Space (1.8-V I/O) Multiplies (32-bit Results) per Clock – Asynchronous 16-Bit Wide EMIF (EMIFA) Cycle or Eight 8 x 8-bit Multiplies (16-Bit With up to 64M-Byte Address Reach Results) per Clock Cycle – Glueless Interface to Asynchronous – Load-Store Architecture With Non-Aligned Memories (SRAM, Flash, and EEPROM) Support – Synchronous Memories (SBSRAM and ZBT – 64 32-bit General-Purpose Registers SRAM) – Instruction Packing Reduces Code Size – Supports Interface to Standard Sync – All Instructions Conditional Devices and Custom Logic (FPGA, CPLD, – Additional C64x+™ Enhancements ASICs, etc) • Protected Mode Operation • Enhanced Direct-Memory-Access (EDMA) • Exceptions Support for Error Detection Controller (64 Independent Channels) and Program Redirection • 3-Port Gigabit Ethernet Switch • Hardware Support for Modulo Loop • Four 64-Bit General-Purpose Timers (Each Auto-Focus Module Operation Configurable as Two 32-Bit Timers) • C64x+ Instruction Set Features • One UART (With RTS and CTS Flow Control) – Byte-Addressable (8-/16-/32-/64-bit Data) • One 4-wire Serial Port Interface (SPI) With Two – 8-bit Overflow Protection Chip-Selects – Bit-Field Extract, Set, Clear • Master/Slave Inter-Integrated Circuit (I2C – Normalization, Saturation, Bit-Counting Bus™) – VelociTI.2 Increased Orthogonality – C64x+ Extensions • Multichannel Audio Serial Port (McASP) • Compact 16-bit Instructions – Ten Serializers and SPDIF (DIT) Mode • Additional Instructions to Support • 16/32-Bit Host-Port Interface (HPI) Complex Multiplies • 32-Bit 33-/66-MHz, 3.3-V Peripheral Component Interconnect (PCI) Master/Slave Interface Conforms to PCI Specification 2.3 • VLYNQ™ Interface (FPGA Interface) • On-Chip ROM Bootloader Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this document. PRODUCT PREVIEW information concerns products in the Copyright © 2007, Texas Instruments Incorporated formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. |
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