COM

Y

Y2

A

INH

Y1

COM

5

2

7

6

1

SW

SW

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An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

SN74LVC2G53

SCES324Q – JULY 2001 – REVISED JANUARY 2019

SN74LVC2G53 Single-Pole Double-Throw (SPDT) Analog Switch

2:1 Analog Multiplexer/Demultiplexer

1

1 Features

1

•

Available in the Texas Instruments

NanoFree™ Package

•

1.65-V to 5.5-V VCC Operation

•

High On-Off Output Voltage Ratio

•

High Degree of Linearity

•

High Speed, Typically 0.5 ns (VCC = 3 V,

CL = 50 pF)

•

Low ON-State Resistance, Typically 6.5

Ω

(VCC = 4.5 V)

•

Latch-Up Performance Exceeds 100 mA Per

JESD 78, Class II

2 Applications

•

Wireless Devices

•

Audio and Video Signal Routing

•

Portable Computing

•

Wearable Devices

•

Signal Gating, Chopping, Modulation or

Demodulation (Modem)

•

Signal Multiplexing for Analog-to-Digital and

Digital-to-Analog Conversion Systems

3 Description

This single 2:1 analog multiplexer/demultiplexer is

designed for 1.65-V to 5.5-V VCC operation.

The SN74LVC2G53 device can handle both analog

and digital signals. This device permits signals with

amplitudes of up to 5.5 V (peak) to be transmitted in

either direction.

NanoFree

package

technology

is

a

major

breakthrough in IC packaging concepts, using the die

as the package.

Applications

include

signal

gating,

chopping,

modulation or demodulation (modem), and signal

multiplexing for analog-to-digital and digital-to-analog

conversion systems.

Device Information(1)

PART NUMBER

PACKAGE

BODY SIZE (NOM)

SN74LVC2G53DCT

SM8 (8)

2.95 mm × 2.80 mm

SN74LVC2G53DCU

VSSOP (8)

2.30 mm × 2.00 mm

SN74LVC2G53YZP

DSBGA (8)

1.91 mm × 0.91 mm

(1) For all available packages, see the orderable addendum at

the end of the data sheet.

Logic Diagram

NOTE: For simplicity, the test conditions shown in

Figure 1 through Figure 4 and Figure 6

through Figure 10 are for the demultiplexer

configuration. Signals can be passed from

COM to Y1 (Y2) or from Y1 (Y2) to COM.

Logic Diagram, Each Switch (SW)