ADC14C080 datasheet(9/17 Pages) NSC

9 / 17 page

ADC14C080 Dynamic Converter Electrical Characteristics (Continued)

Unless otherwise specified, the following specifications apply: AGND = DRGND = 0V, V

A = +3.0V, VDR = +2.5V, Internal VREF

= +1.2V, f

CLK = 80 MHz, VCM =VCMO,CL = 5 pF/pin, . Typical values are for TA = 25˚C. Boldface limits apply for TMIN

≤ T

MAX. All other limits apply for TA = 25˚C (Note 8) (Note 9)

Symbol

Parameter

Conditions

Typical

(Note 10)

Limits

Units

(Limits)

SINAD

Signal-to-Noise and Distortion

Ratio

IN = 10 MHz

dBFS

IN = 70 MHz

71.8

dBFS

IN = 170 MHz

71.4

dBFS

ADC14C080 Logic and Power Supply Electrical Characteristics

Unless otherwise specified, the following specifications apply: AGND = DRGND = 0V, V

A = +3.0V, VDR = +2.5V, Internal VREF

= +1.2V, f

CLK = 80 MHz, VCM =VCMO,CL = 5 pF/pin. Typical values are for TA = 25˚C. Boldface limits apply for TMIN

≤ T

≤

MAX. All other limits apply for TA = 25˚C (Notes 8, 9)

Symbol

Parameter

Conditions

Typical

(Note 10)

Limits

Units

(Limits)

DIGITAL INPUT CHARACTERISTICS (CLK, PD)

IN(1)

Logical “1” Input Voltage

D = 3.6V

2.0

V (min)

IN(0)

Logical “0” Input Voltage

D = 3.0V

0.8

V (max)

IN(1)

Logical “1” Input Current

IN = 3.3V

µA

IN(0)

Logical “0” Input Current

IN = 0V

−10

µA

Digital Input Capacitance

DIGITAL OUTPUT CHARACTERISTICS (D0–D13, DRDY)

OUT(1)

Logical “1” Output Voltage

OUT = −0.5 mA , VDR = 1.8V

1.2

V (min)

OUT(0)

Logical “0” Output Voltage

OUT = 1.6 mA, VDR = 1.8V

0.4

V (max)

Output Short Circuit Source

Current

OUT = 0V

−10

−I

Output Short Circuit Sink Current

OUT =VDR

OUT

Digital Output Capacitance

POWER SUPPLY CHARACTERISTICS

Analog Supply Current

Full Operation

100

mA (max)

Digital Output Supply Current

Full Operation (Note 13)

Power Consumption

Excludes I

DR (Note 13)

300

mW (max)

Power Down Power Consumption

Clock disabled

ADC14C080 Timing and AC Characteristics

Unless otherwise specified, the following specifications apply: AGND = DRGND = 0V, V

A = +3.0V, VDR = +2.5V, Internal VREF

= +1.2V, f

CLK = 80 MHz, VCM =VCMO,CL = 5 pF/pin. Typical values are for TA = 25˚C. Timing measurements are taken at

50% of the signal amplitude. Boldface limits apply for T

MIN

≤ T

MAX. All other limits apply for TA = 25˚C (Notes 8, 9)

Symb

Parameter

Conditions

Typical

(Note 10)

Limits

Units

(Limits)

Maximum Clock Frequency

MHz (max)

Minimum Clock Frequency

MHz (min)

Clock High Time

Clock Low Time

CONV

Conversion Latency

Clock

Cycles

Output Delay of CLK to DATA

Relative to rising edge of CLK

ns (min)

ns(max)

Data Output Setup Time

Relative to DRDY

ns (min)

Data Output Hold Time

Relative to DRDY

ns (min)

Aperture Delay

0.6

Aperture Jitter

0.1

ps rms

ADC14C080 Datasheet(PDF) 9 Page - National Semiconductor (TI)

ADC14C080 Datasheet(HTML) 9 Page - National Semiconductor (TI)

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