1996 Nov 21

14

Philips Semiconductors

Product specification

DTMF/modem/musical-tone generators

PCD3311C; PCD3312C

Table 6

Explanation of time symbols used in Fig.11

8.5.2

Masters generate a bus clock with a maximum frequency of 2 kHz; a minimum LOW period of 105

µs and a minimum

HIGH period of 365

µs. The mark-to-space ratio is 1 : 3 LOW-to-HIGH. Detailed timing is shown in Fig.13, where the two

mode.The time symbols are explained in Table 7.

SYMBOL

PARAMETER

REMARKS

MIN.

MAX.

UNIT

SCL clock frequency

0

100

kHz

tolerable pulse spike width

−

100

ns

bus free time

The time that the bus is free (SDA is HIGH)

before a new transmission is initiated by SDA

going LOW.

4.7

−µs

set-up time repeated START

Only valid for repeated start code.

4.7

−µs

hold time START condition

The time between SDA going LOW and the first

valid negative-going transition of SCL.

4.0

−µs

SCL LOW time

The LOW period of the SCL clock.

4.7

−µs

SCL HIGH time

The HIGH period of the SCL clock.

4.0

−µs

rise time SDA and SCL

−

1.0

µs

fall time SDA and SCL

−

0.3

µs

data set-up time

250

−

ns

data hold time

0

−

ns

set-up time STOP condition

4.0

−µs

Fig.12 Complete data transfer in standard mode.

handbook, full pagewidth

MBC765

9

8

1 - 7

9

8

1 - 7

9

8

1 - 7

STOP

ACK

ADDRESS

R/W

START

CONDITION

ACK

DATA

START

CONDITION

ACK

ADDRESS

R/W

SCL

SDA

Clock LOW minimum = 4.7

µs; clock HIGH minimum = 4 µs.

The dashed line is the acknowledgment of the receiver.

Mark-to-space ratio = 1 : 1 (LOW-to-HIGH).

Maximum number of bytes is unrestricted.

Premature termination of transfer is allowed by generation of STOP condition.

Acknowledge clock bit must be provided by master.