PCD5003USLASH10 datasheet(23/44 Pages) PHILIPS

23 / 44 page

1997 Jun 24

Philips Semiconductors

Product speciﬁcation

Advanced POCSAG Paging Decoder

PCD5003

7.41

SRAM access

The on-chip SRAM can hold up to 96 bytes of call data.

Each call consists of a call header (3 bytes), message data

blocks (3 bytes per codeword) and a call terminator

(3 bytes).

The RAM is filled by the decoder and can be read via the

I2C-bus interface. The RAM is accessed indirectly by

means of a read address pointer and a data output

after the last message byte stored.

Status register bit D2 is set when the read and write

pointers are different. It is reset only when the SRAM

pointers become equal during reading, i.e. when the RAM

becomes empty.

Status bit D3 is set when the read and write pointers

become equal. This can be due to a RAM empty or a RAM

full condition. It is reset after a status read operation.

Interrupts are generated as follows:

• When status bit D2 is set and the receiver is disabled

(RXE = 0): data is available for reading

• Immediately when status bit D3 is set: RAM is either

empty (status bit D2 = 0) or full (status bit D2 = 1).

To avoid loss of data due to RAM overflow at least 3 bytes

of data must be read during reception of the codeword

following the ‘RAM full’ interrupt.

7.42

RAM write address pointer (06H; read)

The RAM write address pointer is automatically

incremented during call reception, as the decoder writes

each data byte to RAM. The RAM write address pointer

can only be read. Values range from 00H to 5FH.

Bit D7 (MSB) is not used and its value is undefined when

read.

7.43

RAM read address pointer (08H; read/write)

The RAM read address pointer is automatically

incremented after reading a data byte via the RAM output

It can be accessed for writing as well as reading.

The values range from 00H to 5FH. When at 5FH a read

operation will cause wrapping around to 00H. Bit D7

(MSB) is not used; it is ignored when written and undefined

when read.

7.44

RAM data output register (09H; read)

The RAM data output register contains the byte addressed

by the RAM read address pointer. It can only be read, each

read operation causing an increment of the RAM read

address pointer.

7.45

EEPROM access

The EEPROM is intended for storage of user addresses

(RICs), sync words and special programmed function

(SPF) bits representing the decoder configuration.

The EEPROM can store 48 bytes of information and is

organized as a matrix of 8 rows by 6 columns.

The EEPROM is accessed indirectly via an address

pointer and a data I/O register.

The EEPROM is protected against inadvertent writing by

means of the programming enable bit in the control

The EEPROM memory map is non-contiguous as can be

seen in Fig.10, which shows both the EEPROM

organization and the access method.

Identiﬁer locations contain RICs or sync words. A total of

20 unassigned bytes is available for general purpose

storage.

7.46

EEPROM address pointer (07H; read/write)

An EEPROM location is addressed via the EEPROM

address pointer. It is incremented automatically each time

a byte is read or written via the EEPROM data I/O register.

The EEPROM address pointer contains two counters, for

the row and the column number. Bits D2 to D0 contain the

column number (0 to 5) and bits D5 to D3 the row number

(0 to 7). Bits D7 and D6 of the address pointer are not

used. Data written to these bits will be ignored, while their

values are undefined when read.

The column and row counters are connected in series.

Upon overflow of the column counter (column = 5) the row

counter is automatically incremented and the column

counter wraps to 0. On overflow the row counter wraps

from 7 to 0.

7.47

EEPROM data I/O register (0AH; read/write)

The byte addressed by the EEPROM address pointer can

be written or read via the EEPROM Data I/O register. Each

access automatically increments the EEPROM address

pointer.

PCD5003U/10 Datasheet(PDF) 23 Page - NXP Semiconductors

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