PCD5043 datasheet(17/24 Pages) PHILIPS

17 / 24 page

1996 Oct 31

Philips Semiconductors

Objective speciﬁcation

DECT burst mode controller

PCD5043

CHARACTERISTICS

Notes to the characteristics

1. VDD = 3.0 V; fclk =13.824 MHz; no external load; one speech link active (under typical conditions).

2. VDD = 3.0 V; fclk =13.824 MHz; no external load; after reset.

3. Maximum differential non-linearity at supply voltage 5.5 V and VREF =1V.

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

Tamb

operating ambient temperature

−25

−

+70

°C

VDD

supply voltage

2.7

−

5.5

VDD(ret)

RAM retention voltage

1.0

−

VDD

IDD

operating supply current

note 1

−

612

IDD(stb)

standby supply current

note 2

−

clock input duty cycle

All inputs LOW except WRN;

XTAL1 running at 14 MHz

−

Digital I/O

VIL

LOW level input voltage

−

0.3VDD

VOL

LOW level output voltage

−

0.3VDD

VIH

HIGH level input voltage

0.7VDD

−

VDD

VOH

HIGH level output voltage

0.7VDD

−

VDD

ILI

input leakage current

1.0

µA

IO(source)

output source current

VDD = 3.6 V;

0.4 V

≤VO ≤ VDD − 0.4 V

2.0

5.0

−

IO(sink)

output sink current

VDD = 3.6 V;

0.4 V

≤VO ≤ VDD − 0.4 V

2.0

5.0

−

IRDYN(sink)

RDYN output sink current

VDD = 3.6 V; VO = 0.4 V

2.0

5.0

−

VDD = 5.0 V; VO = 0.4 V

−

6.0

−

fDCK

DCK input frequency

n=1to32

−

× 64 −

kHz

fFS1

FS1 input frequency

−

kHz

Oscillator (inputs XTAL1 and XTAL2)

transconductance

VDD = 2.7 V

0.6

−−

VDD = 3.6 V

−

1.6

−

feedback resistance

200

500

Ω

RSSI Peak detector (6-bit linear A-D converter, for RSSI measurement on input RSSI_AN)

Vi(RSSI_AN)

input level

−

VDD

Vconv(RSSI_AN) voltage conversion range

−

VREF

Vi(VREF)

VREF input voltage

1.0

3.0

VDD

Zi(VREF)

VREF input impedance

during power-down high

impedance

−

Ω

tconv

conversion time

18.4

−−

µs

integral non-linearity

−−

LSB

differential non-linearity

note 3

−

0.2

1.5

LSB

Zi(RSSI_AN)

input impedance RSSI_AN

−

Ω

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