7 Detailed Description

7.1 Overview

The SN74LVC125A device is a quadruple bus buffer gate featuring independent line drivers with 3-state outputs.

Each output is disabled when the associated output-enable (OE) input is high. When OE is low, the respective

gate passes the data from the A input to its Y output. To ensure the high-impedance state during power up

or power down, OE should be tied to VCC through a pull-up resistor; the minimum value of the resistor is

determined by the current-sourcing capability of the driver.

7.2 Functional Block Diagram

2A

2Y

2OE

1A

1Y

1OE

4A

4Y

4OE

3A

3Y

3OE

7.3 Feature Description

• Wide operating voltage range

– Operates from 1.65V to 5.5V

• Allows down voltage translation

• Inputs accept voltages to 5.5V

7.4 Device Functional Modes

Table 7-1. Function Table

INPUTS

OUTPUT

Y

OE

A

L

H

H

L

L

L

H

X

Z

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SN74LVC125A

SCAS290R – JANUARY 2015 – REVISED FEBRUARY 2024

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