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ST92F124 Datasheet(PDF) 388 Page - STMicroelectronics |
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ST92F124 Datasheet(HTML) 388 Page - STMicroelectronics |
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388 / 429 page  388/429 ST92F124/F150/F250 - ELECTRICAL CHARACTERISTICS EXTERNAL BUS TIMING TABLE (MC=1) (VDD = 5V ± 10%, TA = –40°C to +125°C, CLoad = 0 to 50pF Notes: The expressions in the “Formula” column show how to calculate the typical parameter value depending on the CPU clock period and the number of inserted wait cycles. The values in the Min column give the parameter values for a CPU clock at 12MHz and two wait states for T1 and T2. For certain versions of the ST92F150, the external bus has high-drive capabilities. Legend: Tck = INTCLK period = OSCIN period when OSCIN is not divided by 2; = 2*OSCIN period when OSCIN is divided by 2; = OSCIN period / PLL factor when the PLL is enabled TckH = INTCLK high pulse width (normally = Tck/2, except when INTCLK = OSCIN, in which case it is OSCIN high pulse width) TckL = INTCLK low pulse width (normally = Tck/2, except when INTCLK = OSCIN, in which case it is OSCIN low pulse width) P = clock prescaling value (=PRS; division factor = 1+P) Wa = wait cycles on ALE; = max (P, programmed wait cycles in EMR2, requested wait cycles with WAIT) Wd = wait cycles on OEN and WEN ; = max (P, programmed wait cycles in WCR, requested wait cycles with WAIT) N° Symbol Parameter Value (see note) Unit Formula Min Max 1 TsA (ALE) Address Set-up Time before ALE ↓ Tck*Wa+TckH - 48 160 ns 2 ThALE (A) Address Hold Time after ALE ↓ TckL - 31 10 ns 3 TwALE ALE High Pulse Width Tck*Wa+TckH - 58 150 ns 4 TdAz (OEN) Address Float (P0) to OEN ↓ 00 ns 5 TdOEN(Az) P0 driven after OEN ↑ TckL - 13 29 ns 6TwOEN OEN Low Pulse Width Tck*Wd+TckH - 36 172 ns 7TwWEN WEN Low Pulse Width Tck*Wd+TckH - 36 172 ns 8 TdOEN (DR) OEN ↓ to Data Valid Delay Tck*Wd+TckH - 44 164 ns 9 ThDR (OEN) Data hold time after OEN ↑ 00 ns 10 ThOEN(A) Address (A21:A8) hold time after OEN ↑ 00 ns 11 ThWEN(A) Address (A21:A8) hold time after WEN ↑ 00 ns 12 TvA(OEN) Address (A21:A0) valid to OEN ↑ Tck (Wd+Wa+1.5) - 76 382 ns 13 TvA(WEN) Address (A21:A0) valid to WEN ↑ Tck (Wd+Wa+1.5) - 44 414 ns 14 TsD (WEN) Data Set-up time before WEN ↑ Tck*Wd+TckH - 158 50 ns 15 ThWEN(DW) Data Hold Time after WEN ↑ TckL - 37 5 ns 16 TdALE (WEN) ALE ↑ to WEN ↑ Delay Tck (Wd+Wa+1.5) - 54 404 ns 17 TdALE (OEN) ALE ↑ to OEN ↑ Delay Tck (Wd+Wa+1.5) - 50 408 ns 1 |
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