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ST92F124/F150/F250 - KNOWN LIMITATIONS

13 KNOWN LIMITATIONS

Limitations described in this section apply to all sil-

icon revisions. They are listed in the following ta-

ble.

Additional limitations exist on specific silicon revi-

sions identified by the following trace codes:

– ST92F124 Gxxxxxxxx1

or 1 ST92F124 xxxxx VG

– ST92F150 AxxxxxxxxZ

– ST92F150 AxxxxxxxxY

or Y ST92F150 xxxxx VA

– ST92F250 AxxxxxxxxA

or A ST92F250 xxxxx VA

Please contact your nearest sales office for further

information.

Table 74. List of limitations

13.1 FLASH ERASE SUSPEND LIMITATIONS

13.1.1 Description

In normal operation, the FSUSP bit (bit 2 in the

FCR register) must be set to suspend the current

Sector Erase operation in Flash memory in order

to access a sector not being erased. The Flash

sector erase operation is done in 3 different steps:

1. Program all addresses to 0 on selected sectors

2. Erase and erase verify

3. Reprogramming

If the erase suspend is performed during Steps 1

and 2, the flash works correctly. If the erase sus-

pend is performed during Step 3, the PGER bit (bit

6 in the FESR1 register) is set although no pro-

gram error occurred.

13.1.2 Workaround

After a Sector Erase suspend operation, the soft-

ware must check the status register to detect if an

erase error occurred (the corresponding sector

must be discarded). Then the software must reset

the FEERR bit. This automatically resets the flash

status register.

Whatever the state of the PGER bit at the end of

the erase operation, it will not impact the applica-

tion and an erase error is still detected.

Section

Limitation

Section 13.1

“FLASH ERASE SUSPEND LIMITATIONS

Section 13.2

“FLASH CORRUPTION WHEN EXITING STOP MODE

Section 13.3

“I2C LIMITATIONS

Section 13.4

“SCI-A AND CAN INTERRUPTS

Section 13.5

“SCI-A MUTE MODE

Section 13.6

“CAN FIFO CORRUPTION WHEN 2 FIFO MESSAGES ARE PENDING

Section 13.7

“MFT DMA MASK BIT RESET WHEN MFT0 DMA PRIORITY LEVEL IS SET TO 0

Section 13.8

“EMULATION CHIP LIMITATIONS

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