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ST92F124 Datasheet(PDF) 412 Page - STMicroelectronics |
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ST92F124 Datasheet(HTML) 412 Page - STMicroelectronics |
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412 / 429 page ![]() 412/429 ST92F124/F150/F250 - KNOWN LIMITATIONS KNOWN LIMITATIONS (Cont’d) 13.3.3 AF bit (acknowledge failure flag) in transmitter mode (slave and master) Description The AF bit is cleared by reading the I2CSR2 reg- ister. However, if read before the completion of the transmission, the AF flag will be set again, thus possibly generating a new interrupt. Workaround Software must ensure either that the SCL line is back at 0 before reading the SR2 register, or be able to correctly handle a second interrupt during the 9th pulse of a transmitted byte. 13.3.4 BUSY flag in multimaster mode Description The BUSY flag is NOT updated when the interface is disabled (PE=0). This can have consequences when operating in Multimaster mode; i.e. a second active I2C master commencing a transfer with an unset BUSY bit can cause a conflict resulting in lost data. Workaround Check that the I2C is not busy before enabling the I2C Multimaster cell. 13.3.5 ARLO (arbitration lost) flag in multimaster mode Description In a Multimaster environment, when the interface is configured in Master Receive mode it does not perform arbitration during the reception of the Ac- knowledge Bit. Mishandling of the ARLO bit from the I2CSR2 register may occur when a second master simultaneously requests the same data from the same slave and the I2C master does not acknowledge the data. The ARLO bit is then left at 0 instead of being set. Workaround None 13.3.6 BUSY flag gets cleared when BUS error occurs Description BUSY bit gets cleared when the BUS error occurs but the bus is actually BUSY (SCL line shows CLK pulses). Contradictory, M/SL bit is unaffected on BUS error Workaround If a Bus Error occurs, a Stop or a repeated Start condition should be generated by the Master to re- synchronize communication, get the transmission acknowledged and the bus released for further communication 1 |
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