ST92F124 datasheet(413/429 Pages) STMICROELECTRONICS

413 / 429 page

413/429

ST92F124/F150/F250 - KNOWN LIMITATIONS

KNOWN LIMITATIONS (Cont’d)

13.4 SCI-A AND CAN INTERRUPTS

Description

SCI-A interrupt (I0 channel) and CAN interrupts

(channels E0, E1, F0, F1, G0, G1, H0, H1) do not

respond when the CPUCLK is prescaled (MODER

Workaround

Avoid using CPU prescaler when SCI-A and/or

CAN interrupts are used in the application.

13.5 SCI-A MUTE MODE

13.5.1 Mute Mode Description

The SCI can be put in Mute mode waiting for an

Idle line detection or an Address Mark detection,

and discarding all other byte transmissions. This is

done by setting the RWU (Receiver wake-up) bit in

the SCICR2 register (R244, page 26). This bit can

be reset either by software, to leave the Mute

mode, or by hardware when a wake up condition

has been reached.

A received data is indicated by the RDRF (Read

Data Ready Flag) bit in the SCISR register (R240,

page 26). This status bit is evaluated at the end of

the stop bit. If the RWU bit is in the set state at the

end of the stop bit, the data is not loaded in the

data register and the RDRF bit is not set.

On the contrary, if the RWU bit is in the reset state

at the end of the stop bit the data is loaded in the

data register and the RDRF bit is set.

13.5.2 Limitation Description

The SCICR2 also contains the following configura-

tion bits: Interrupt Enable, Transmitter Enable, Re-

ceiver Enable and Send Break.

When the value of one of these bits is modified by

software, the SCICR2 register is read, its value is

modified and reloaded in the SCICR2 register. If

the SCI-A is in Mute mode during the read opera-

tion (RWU=1) and if an address mark event occurs

(resetting the RWU bit) before the write operation,

the RWU bit is set before the end of the stop bit. In

this case, the RDRF bit is not set, the data is not

received and no flag indicates the lost of the data.

Figure 1. Mute Mode Mechanism on address mark

Consequence

The address byte is lost and the SCI-A is again in

Mute mode.

13.5.3 Workaround

If you need to disable the SCI-A interrupt while it is

in Mute mode, use the global interrupt mask in the

dedicated interrupt controller, refer to Section 5.7

“Standard Interrupts” in the datasheet. Do not

change the TE, RE and SBK bits in the SCICR2

data

Data Line

RWU

RDRF

data

Data Line

RWU

RDRF

ld r0,SCICR2

and r0,0x80

ld SCICR2, r0

Corrupted Mute mode mechanism

Mute mode mechanism

int

under an SCICR2 access

ST92F124 Datasheet(PDF) 413 Page - STMicroelectronics

ST92F124 Datasheet(HTML) 413 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL