ST92F124 datasheet(417/429 Pages) STMICROELECTRONICS

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ST92F124/F150/F250 - KNOWN LIMITATIONS

KNOWN LIMITATIONS (Cont’d)

TCAN frame: This is minimum CAN frame duration

Figure 4. Critical Window Timing Diagram

Figure 5. Reception of a Sequence of Frames

Side-effect of Workround 1

Because the while loop lasts 16 CPU cycles, if

fCPU≤16MHz at high baud rate, it is possible to

miss a dominant state on the bus if it lasts just one

CAN bit time and the bus speed is high enough

(see Table 75)

Table 75. While Loop Timing

Note: As can be seen from the above table, no

side effect occurs in cases when fCPU is 16MHz or

higher and if the CAN baud rate is below 1MBaud.

If this happens, we will continue waiting in the

while loop instead of releasing the FIFO immedi-

ately. The workaround is still valid because we will

not release the FIFO during the critical period. But

the application may lose additional time waiting in

the while loop as we are no longer able to guar-

antee a maximum of 6 CAN bit times spent in the

workaround.

In this particular case the time the application can

spend in the workaround may increase up to a full

CAN frame, depending of the frame contents. This

case is very rare but happens when a specific se-

quence is present on in the CAN frame.

The example in Figure 6 shows reception if TCAN

is 12/fCPU and the sampling time is 16/fCPU.

If the application is using the maximum baud rate

and the possible delay caused by the workaround

is not acceptable, there is another workaround

which reduces the Rx pin sampling time.

A release is not

allowed at this time

Critical window: the received

message is placed in the FIFO

CAN Frame

Acknowledge: last

dominant bit in the frame

Time to test RX pin and to

release the FIFO 4.5 µs@4MHz Time between the end of the

acknowledge and the critical windows

- 6 full CAN bit times+ time to the sample point

approx. 13µs @ 500kBd

TCAN frame 1TCAN frame 2TCAN frame 3

FMP

BUS

CPU

TIT disable

TIT higher level

TIT CAN

fCPU

Baud rate for possible

missed dominant bit

24 MHz

No dominant bit missed

16 MHz

1 MBaud

8 MHz

> 500 kHz

4 MHz

> 250 kHz

fCPU

> fCPU / 16

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