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PCF50732 Datasheet(PDF) 22 Page - NXP Semiconductors |
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PCF50732 Datasheet(HTML) 22 Page - NXP Semiconductors |
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22 / 64 page  1999 May 03 22 Philips Semiconductors Objective specification Baseband and audio interface for GSM PCF50732 After conversion the corresponding bit in the AUXADC flag register is reset (see Table 18). If RXON is activated during an auxiliary analog-to-digital conversion cycle, the auxiliary conversion is interrupted and restarted when RXON returns LOW, indicating no receive burst activity. When register AUXADC1A is read, a battery voltage measurement during a transmission burst is executed. The PCF50732 waits for a rising edge of TXON, and powers up the receive path. After the settling time of the ADC added to the programmed AUXADC conversion delay (in 48 MCLK cycles) has elapsed, valid data is available and stored in the AUXADC1A register. Fig.10 Typical transfer characteristics of AUXADC (output code as function of differential input voltage). handbook, full pagewidth MGR996 0 1440 0.2 output code (LSB) offset at 0 V gain tolerance 0 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 Vin (V) |
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