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PCF84C00T Datasheet(PDF) 9 Page - NXP Semiconductors

Part # PCF84C00T
Description  8-bit microcontroller with I2C-bus interface
PDF  24 Pages
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Manufacturer  PHILIPS [NXP Semiconductors]
Direct Link  http://www.nxp.com
Logo PHILIPS - NXP Semiconductors

PCF84C00T Datasheet(HTML) 9 Page - NXP Semiconductors

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1996 Nov 25
9
Philips Semiconductors
Product specification
8-bit microcontroller with I2C-bus interface
PCF84C00
6
FUNCTIONAL DESCRIPTION
6.1
‘Piggy-back’ version PCF84C00B
The PCF84C00B package has standard pinning on the
bottom to facilitate insertion as a mask-programmed
device. An EPROM can be mounted on top in an additional
socket. The total package height is greater than the height
of a standard DIP package. The PCF84C00B can address
up to 8 kbytes of external ROM/RAM, and has 256 bytes
of internal data RAM.
6.2
ROM-less version PCF84C00T
The PCF84C00T microcontroller contains no on-chip
ROM, but has all address and data lines brought out to
access an external ROM or EPROM. Consequently, this
version has more pins (see Fig.5) than the devices in the
PCF84CxxxA family with on-chip or ‘piggy-back’ ROM.
The PCF84C00T can address up to 8 kbytes of external
program memory, and has 256 bytes of internal data RAM.
6.3
Data memory
Data memory consists of 256 bytes of Random-Access
Memory (RAM). All locations are indirectly addressable
using RAM pointer registers; up to 16 designated locations
are directly addressable. Memory also includes an 8-level
program counter stack addressed by a 3-bit stack pointer.
6.4
I/O facilities
Each device has 23 I/O lines arranged as follows:
• Port 0; 8-bit parallel port (P0.0-P0.7)
• Port1; 8-bit parallel port (P1.0-P1.7)
• Port 2; 4-bit parallel port (P2.0-P2.3)
• SCLK ; I2C-bus (serial I/O) clock line
• INT/T0; External interrupt and test input. When used as
a test input, it can be directly tested by conditional
branch instructions JT0 and JNT0.
• T1; Test input which can alter program sequences when
tested by conditional jump instructions JT1 and JNT1.
T1 also functions as an input to the 8-bit timer/event
counter.
6.5
Reset
A positive-going signal on the RESET input/output:
• Sets the program counter to zero
• Selects location 0 of memory bank 0 and register bank 0
• Sets the stack pointer to zero (000); pointing to RAM
address 8
• Disables the interrupts (external, timer and I2C-bus)
• Stops the timer/event counter, then sets it to zero
• Sets the timer prescaler to divide by 32
• Resets the timer flag
• Sets all ports except P2.3 to input mode
• Sets the I2C-bus interface to slave receiver mode and
disables the I2C-bus interface
• Cancels Idle and Stop mode.
A negative-going signal on the RESET input/output:
• Sets P2.3/SDA and SCLK to HIGH after a maximum of
30 clock pulses
• Sets the I2C-bus interface to slave receiver mode and
disables the I2C-bus interface after a maximum of 30
clock pulses
• Starts program execution after 1866 clock pulses.
7
LIMITING VALUES
Limiting values in accordance with the Absolute Maximum Rating System (IEC 134).
SYMBOL
PARAMETER
CONDITIONS
MIN.
MAX.
UNIT
VDD
supply voltage
−0.8
+8
V
VI
all input voltages
−0.5
VDD+0.5 V
II
DC input current
−10
+10
mA
IO
DC output current
−10
+10
mA
Ptot
total power dissipation
−
125
mW
Tstg
storage temperature
−65
+150
°C



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