PCF8573T datasheet(14/24 Pages) PHILIPS

14 / 24 page

1997 Mar 28

Philips Semiconductors

Product speciﬁcation

Clock/calendar with Power Fail Detector

PCF8573

12 DC CHARACTERISTICS

VSS2 =0V; Tamb = −40 to + 85 °C unless otherwise speciﬁed. Typical values at Tamb =25 °C.

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNI

Supply

VDD − VSS2 supply voltage (I2C interface)

2.5

5.0

6.0

VDD − VSS1 supply voltage (clock)

tHD; DAT ≥ 300 ns

1.1

1.5

VDD − VSS2

ISS1

supply current

at VSS1 (pin 15)

see Fig.11

VDD − VSS1 = 1.5 V

−−3

−10

µA

VDD − VSS1 =5V

−−12

−50

µA

ISS2

supply current

at VSS2 (pin 8)

VDD − VSS2 =5V;

IO = 0 all outputs

−−

−50

µA

Input SCL, input/output SDA

VIL

LOW level input voltage

−−

0.3VDD

VIH

HIGH level input voltage

0.7VDD

−−

ILI

input leakage current

VI =VSS2 or VDD

−1

−

µA

input capacitance

−−

7pF

Inputs A0, A1, TEST

VIL

LOW level input voltage

−−

0.2VDD

VIH

HIGH level input voltage

0.7VDD

−−

ILI

input leakage current

VI =VSS2 or VDD

−250

−

+250

Inputs EXTPF, PFIN

VIL

LOW level input voltage

−

0.2VDD − VSS1 V

VIH

HIGH level input voltage

0.7VDD − VSS1 −−

ILI

input leakage current

VI =VSS1 to VDD

−1.0

−

+1.0

µA

VI =VSS1 to VDD;

Tamb =25 °C

−0.1

−

+0.1

µA

Output SDA (n channel open-drain)

VOL

LOW level output voltage

output ON; IO = 3 mA;

VDD − VSS2 = 2.5 to 6 V

−−

0.4

ILI

input leakage current

VDD − VSS2 =6V;

VO =6V

−1.0

−

+1.0

µA

Output SEC, MIN, COMP, FSET (normal buffer outputs)

VOL

LOW level output voltage

VDD − VSS2 = 2.5 V;

IO = 0.3 mA

−−

0.4

VDD − VSS2 =4to6V;

IO = 1.6 mA

−−

0.4

VOH

HIGH level output voltage

VDD − VSS2 = 2.5 V;

IO = −0.1 mA

VDD − 0.4

−−

VDD − VSS2 =4to6V;

IO = −0.5 mA

VDD − 0.4

−−

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