PCF8583P datasheet(12/28 Pages) PHILIPS

12 / 28 page

1997 Jul 15

Philips Semiconductors

Product speciﬁcation

Clock/calendar with 240

× 8-bit RAM

PCF8583

Fig.10 Alarm control register, event-counter mode.

handbook, full pagewidth

memory location 08

reset state: 0000 0000

timer function :

000

no timer

001

units

010

100

011

10 000

100

1 000 000

101

not allowed

110

not allowed

111

test mode, all counters

in parallel

timer interrupt enable :

timer flag, no interrupt

timer flag, interrupt

clock alarm function :

no event alarm

event alarm

not allowed

timer alarm enable :

no timer alarm

timer alarm

alarm interrupt enable :

alarm flag, no interrupt

alarm flag, interrupt

654

321

MSB

LSB

MRB007

In the clock mode, if the alarm enable is not activated

(alarm enable bit of control/status register is logic 0), the

interrupt output toggles at 1 Hz with a 50% duty cycle (may

be used for calibration). This is the default power-on state

of the device. The OFF voltage of the interrupt output may

exceed the supply voltage, up to a maximum of 6.0 V.

A logic diagram of the interrupt output is shown in Fig.11.

7.10

Oscillator and divider

A 32.768 kHz quartz crystal has to be connected to OSCI

(pin 1) and OSCO (pin 2). A trimmer capacitor between

OSCI and VDD is used for tuning the oscillator (see quartz

frequency adjustment). A 100 Hz clock signal is derived

from the quartz oscillator for the clock counters.

In the 50 Hz clock mode or event-counter mode the

oscillator is disabled and the oscillator input is switched to

a high impedance state.

This allows the user to feed the 50 Hz reference frequency

or an external high speed event signal into the input OSCI.

7.11

Initialization

When power-up occurs the I2C-bus interface, the

control/status register and all clock counters are reset.

The device starts time-keeping in the 32.768 kHz clock

mode with the 24 h format on the first of January at

0.00.00: 00. A 1 Hz square wave with 50% duty cycle

appears at the interrupt output pin (starts HIGH).

It is recommended to set the stop counting flag of the

control/status register before loading the actual time into

the counters. Loading of illegal states may lead to a

temporary clock malfunction.

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