5

AT24C01A/02/04/08A/16A

5092C–SEEPR–2/07

Note:

2. This parameter is characterized.

Device Operation

CLOCK and DATA TRANSITIONS: The SDA pin is normally pulled high with an exter-

nal device. Data on the SDA pin may change only during SCL low time periods (see to

Figure 4 on page 7). Data changes during SCL high periods will indicate a start or stop

condition as defined below.

START CONDITION: A high-to-low transition of SDA with SCL high is a start condition

which must precede any other command (see to Figure 5 on page 7).

STOP CONDITION: A low-to-high transition of SDA with SCL high is a stop condition.

After a read sequence, the stop command will place the EEPROM in a standby power

mode (see Figure 5 on page 7).

ACKNOWLEDGE: All addresses and data words are serially transmitted to and from

the EEPROM in 8-bit words. The EEPROM sends a “0” to acknowledge that it has

received each word. This happens during the ninth clock cycle.

STANDBY MODE: The AT24C01A/02/04/08A/16A features a low-power standby mode

which is enabled: (a) upon power-up and (b) after the receipt of the STOP bit and the

completion of any internal operations.

Table 5. AC Characteristics

100 pF (unless otherwise noted)

Symbol

Parameter

AT24C01A/02/04/08A/16A

Units

Min

Max

Clock Frequency, SCL

400

kHz

Clock Pulse Width Low

1.2

µs

Clock Pulse Width High

0.6

µs

50

ns

Clock Low to Data Out Valid

0.1

0.9

µs

Time the bus must be free before

1.2

µs

Start Hold Time

0.6

µs

Start Set-up Time

0.6

µs

Data In Hold Time

0

µs

Data In Set-up Time

100

ns

300

ns

300

ns

Stop Set-up Time

0.6

µs

Data Out Hold Time

50

ns

Write Cycle Time

5

ms

5.0V, 25

°C, Page Mode

1M

Write Cycles