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AT90USB646 Datasheet(PDF) 51 Page - ATMEL Corporation |
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AT90USB646 Datasheet(HTML) 51 Page - ATMEL Corporation |
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51 / 435 page  51 7593D–AVR–07/06 AT90USB64/128 Figure 6-4. PLL Clocking System 6.11.2 PLL Control and Status Register – PLLCSR • Bit 7..5 – Res: Reserved Bits These bits are reserved bits in the AT90USB64/128 and always read as zero. • Bit 4..2 – PLLP2:0 PLL prescaler These bits allow to configure the PLL input prescaler to generate the 2MHz input clock for the PLL. • Bit 1 – PLLE: PLL Enable When the PLLE is set, the PLL is started. 8 MHz RC OSCILLATOR XTAL1 XTAL2 OSCILLATORS PLL 24x PLLE Lock Detector PLOCK clkUSB (48MHz) PLL clock Prescaler System Clock clk 2MHz OSCILLATOR Watchdog Bit 7 65 43 21 0 $29 ($29) PLLP2 PLLP1 PLLP0 PLLE PLOCK PLLCSR Read/Write RR R R RR R/W R Initial Value 0 0 0 0 0 0 0/1 0 Table 6-13. PLL input prescaler configurations PLLP2 PLLP1 PLLP0 Clock Division Factor External XTAL required for USB operation (MHz) 000 Reserved - 001 Reserved - 010 Reserved - 011 4 8 100 Reserved - 101 Reserved - 110 8 16 111 Reserved - |
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