Philips Semiconductors

Product specification

PCK2010R

CK98R (100/133MHz) RCC spread spectrum

system clock generator

1999 Oct 19

10

AC CHARACTERISTICS (Continued)

TEST CONDITIONS

LIMITS

SYMBOL

PARAMETER

TEST CONDITIONS

UNIT

NOTES

SYMBOL

PARAMETER

Measurement loads

(lumped)

Measure points

MIN

TYP

MAX

UNIT

NOTES

CPUCLK to 3V66 CLK,

CPU leads

CPU@20 pF,

3V66@30 pF

CPU@1.25 V,

3V66@1.5 V

0.0

0.45

1.5

ns

1

3V66 CLK to PCICLK,

3V66 leads

3V66@30 pF,

PCI@30 pF

3V66@1.5 V,

PCI@1.5 V

1.5

2.0

3.5

ns

1

CPUCLK to IOAPIC,

CPU leads

CPU@20 pF,

IOAPIC@20 pF

3CPU@1.25 V,

IOAPIC@1.25 V

1.5

2.4

4.0

ns

1

CPUCLK to PCICLK ,

CPU leads

CPU@20 pF

PCI@30 pF

CPU@1.25 V

PCI@1.5 V

1.5

3.8

4.0

ns

CPUDIV2 to CPUCLK,

CPUDIV2 leads

CPUDIV2@20 pF

CPU@20 pF

CPUDIV2@

CPU@1.25 V

0.0

1.6

2.5

ns

NOTES:

2. Period, jitter, offset and skew measured on rising edge @1.25 V for 2.5 V clocks and @ 1.5 V for 3.3 V clocks.

3. The PCICLK is the CPUCLK divided by four at CPUCLK = 133 MHz. The 3V66 CLK is internal VCO frequency divided by three at

CPUCLK = 100 MHz.

4. 3V66 CLK is internal VCO frequency divided by two at CPUCLK = 133 MHz. The 3V66 CLK is internal VCO frequency divided by three at

CPUCLK = 100 MHz.

stable and operating within specification.

9. The average period over any 1

µs period of time must be greater than the minimum specified period.

10. Calculated at minimum edge-rate (1V/ns) to guarantee 45/55% duty-cycle. Pulse width is required to be wider at faster edge-rate to ensure

duty-cycle specification is met.

11. Output (see Figure 5 for measure points).