VDD

Logic High

INPUT

VIH

STATE

Tied to VDD

CONNECTION

VIL

Tied to GND

Logic Low

RPD

ESD

Logic level input pin

Figure 8-1. Logic Level Input PIn

VDD

Inactive

OUTPUT

No Fault

STATE

Pulled-Up

STATUS

Fault

Pulled-Down

Active

RPU

ESD

Shows the structure of the open-drain output pin, nFAULT. The open-drain output requires an external pullup resistor to function

properly.

Figure 8-2. Open Drain Output Pin (ST)

8.3.2 Programmable Current Limit

The TPS274C65CP integrates an adjustable current limit feature. With external resistor at ILIMCFG pin, the

current limit of the device can be adjusted. When the overload or short-circuit situation happens, the device

clamps the current at preset current limit level.

A lower current limit lowers fault energy and current during a load failure event such as a short-circuit or a partial

load failure. By lowering fault energy and current, the overall system improves through:

• Reduced size and cost in current carrying components such as PCB traces and module connectors

• Less disturbance at the power supply (VS pin) during a short circuit event

• Less additional budget for the power supply to account for overload currents in one channel or more

• Improved protection of the downstream load

Table 8-1. ILIMCFG Table for TPS274C65CP

Resistor Value (kΩ)(1)

Typical ILIM Threshold (A)

13.3

0.25

17.8

0.4

23.7

0.56

31.6

0.72

44.2

1

59

1.25

78.7

1.6

110

1.9

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TPS274C65CP

SLVSH35A – OCTOBER 2023 – REVISED FEBRUARY 2024

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