ams Datasheet

Page 21

[v1-08] 2017-Aug-28

Document Feedback

TSL2584TSV − Register Description

ADC Channel Data Registers (14h-17h)

The ADC Channel data are expressed as 16-bit values spread

across two registers. The ADC Channel 0 data registers,

DATA0LOW and DATA0HIGH provide the lower and upper bytes,

respectively, of the ADC value of Channel 0. Registers

DATA1LOW and DATA1HIGH provide the lower and upper bytes,

respectively, of the ADC value of Channel 1. All Channel data

registers are read-only and default to 00h on power up.

Figure 25:

ADC Channel Data Registers

Note(s):

1. The Read Word protocol can be used to read byte-paired registers. For example, the DATA0LOW and DATA0HIGH registers (as well

as the DATA1LOW and DATA1HIGH registers) may be read together to obtain the 16-bit ADC value in a single transaction.

The upper byte data registers can only be read following a read

to the corresponding lower byte register. When the lower byte

register is read, the upper eight bits are strobed into a shadow

register, which is read by a subsequent read to the upper byte.

The upper register will read the correct value even if additional

ADC integration cycles end between the reading of the lower

and upper registers.

Register

Address

Bits

Description

DATA0LOW

14h

7:0

ADC Channel 0 lower byte

DATA0HIGH

15h

7:0

ADC Channel 0 upper byte

DATA1LOW

16h

7:0

ADC Channel 1 lower byte

DATA1HIGH

17h

7:0

ADC Channel 1 upper byte