ADIS16204SLASHPCBZ datasheet(5/24 Pages) AD

5 / 24 page

ADIS16204

Rev. 0 | Page 5 of 24

TIMING SPECIFICATIONS

TA = +25°C, VCC = +3.3 V, unless otherwise noted.

Table 2.

Parameter

Description

Min1

Typ

Max1

Unit

fSCLK

Fast mode2

0.01

2.5

MHz

Normal mode2

0.01

1.0

MHz

tDATARATE

Chip select period, fast mode2

μs

Chip select period, normal mode2

100

μs

tCSHIGH

Chip select high

1/fSCLK

tCS

Chip select to clock edge

48.8

tDAV

Data output valid after SCLK edge

100

tDSU

Data input setup time before SCLK rising edge

24.4

tDHD

Data input hold time after SCLK rising edge

48.8

tDF

Data output fall time

12.5

tDR

Data output rise time

12.5

tSFS

CS high after SCLK edge

1 Guaranteed by design; typical specifications are not tested or guaranteed.

2 Based on sample rate selection.

SCLK

tDATARATE

Figure 2. SPI Chip Select Timing

SCLK

DOUT

DIN

W/R

MSB

DB14

LSB

DB13

DB12

DB10

DB11

DB2

LSB

DB1

tCS

tSFS

tDAV

tDHD

tDSU

Figure 3. SPI Timing

(Utilizing SPI Settings Typically Identified as Phase = 1, Polarity = 1)

ADIS16204/PCBZ Datasheet(PDF) 5 Page - Analog Devices

ADIS16204/PCBZ Datasheet(HTML) 5 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

Datasheet Download

Link URL