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REGISTER DESCRIPTION

CDCE401

SCAS820 – JUNE 2006

WORD 0:

BIT

NAME

DESCRIPTION/FUNCTION

TYPE

DEFAULT

0

C0

Register selection

W

0

1

C1

Register selection

W

0

2

CXI0

Load capacitance XIN, bit 0

W

0

3

CXI1

Load capacitance XIN, bit 1

W

0

4

CXI2

Load capacitance XIN, bit 2

W

0

5

CXI3

Load capacitance XIN, bit 3

W

0

6

CXI4

Load capacitance XIN, bit 4

W

0

7

CXI5

Load capacitance XIN, bit 5

W

1

8

CXI6

Load capacitance XIN, bit 6

W

1

9

CXI7

Load capacitance XIN, bit 7

W

0

WORD 1:

BIT

NAME

DESCRIPTION/FUNCTION

TYPE

DEFAULT

0

C0

Register selection

W

1

1

C1

Register selection

W

0

2

CXO0

Load capacitance XOUT, bit 0

W

0

3

CXO1

Load capacitance XOUT, bit 1

W

0

4

CXO2

Load capacitance XOUT, bit 2

W

0

5

CXO3

Load capacitance XOUT, bit 3

W

0

6

CXO4

Load capacitance XOUT, bit 4

W

0

7

CXO5

Load capacitance XOUT, bit 5

W

1

8

CXO6

Load capacitance XOUT, bit 6

W

1

9

CXO7

Load capacitance XOUT, bit 7

W

0

WORD 2:

BIT

NAME

DESCRIPTION/FUNCTION

TYPE

DEFAULT

0

C0

Register selection

W

0

1

C1

Register selection

W

1

2

PD0

Post-divider selection, bit 0

W

0

3

PD1

Post-divider selection, bit 1

W

0

4

PD2

Post-divider selection, bit 2

W

0

5

OG0

W

1

6

OG1

W

1

7

OP0

W

0

8

OP1

W

0

9

OP2

W

0

(1)

bits OP[2:0] are used to set the bias point of the oscillator core stage. In combination with setting the post-divider ratio PD[2:0] = 111,

the current consumption can be optimized to set oscillator core current consumption for lower frequencies and higher frequencies. This

ensures that the oscillator core is in operating optimally for phase noise and low XTAL-drive power. Setting core power too high impacts

XTAL-drive power, which affects the lifetime of the crystal.

9

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