56855 datasheet(39/52 Pages) FREESCALE

Part #	56855

Description	16-bit Digital Signal Controllers

PDF	52 Pages

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Manufacturer	FREESCALE [Freescale Semiconductor, Inc]

Direct Link	http://www.freescale.com

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Enhanced Synchronous Serial Interface (ESSI) Timing

56855 Technical Data, Rev. 6

Freescale Semiconductor

Figure 4-25 Slave Mode Clock Timing

3. All the timings for the ESSI are given for a non-inverted serial clock polarity (TSCKP=0 in SCR2 and RSCKP=0 in SCSR)

and a non-inverted frame sync (TFSI=0 in SCR2 and RFSI=0 in SCSR). If the polarity of the clock and/or the frame sync have

been inverted, all the timings remain valid by inverting the clock signal SCK/SC0 and/or the frame sync SC2/SC1 in the tables

and in the figures.

4. 50 percent duty cycle

5. bl = bit length; wl = word length

tTHS

tTSS

tHS

tSS

tRFSWLS

tRFSWHS

tRFBLS

tRFSBHS

tTXHIS

tTXNVS

tFTXVS

tTXVS

tFTXES

tTXES

tTFSWLS

tTFSWHS

tTFSBLS

tTFSBHS

tSCKL

tSCKW

tSCKH

First Bit

Last Bit

SCK input

SC2 (bl) input

SC2 (wl) input

STD

SC0 input

SC1 (bl) input

SC1 (wl) input

SRD

56855 Datasheet(PDF) 39 Page - Freescale Semiconductor, Inc

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